WM8281ECSSLASHR datasheet(383/392 Pages) CIRRUS

383 / 392 page

WM8281

Rev 4.0

383

RESETS SUMMARY

The contents of Table 134 provide a summary of the WM8281 registers and other programmable

memory under different reset conditions. The associated events and conditions are listed below.



A Power-On Reset occurs when AVDD or DBVDD1 is below its respective reset threshold.

(Note that DCVDD is also required for initial start-up; subsequent interruption to DCVDD

should only be permitted as part of a control sequence for entering Sleep mode.)



A Hardware Reset occurs when the RESET

¯¯¯¯¯¯ input is asserted (logic 0).



A Software Reset occurs when register R0 is written to.



Sleep Mode is selected when LDO1 is disabled. (LDO1 can be controlled using the

LDO1_ENA register bit, or using the LDOENA pin; both of these controls must be de-

asserted to disable the LDO.) Note that the AVDD, DBVDD1 and LDOVDD supplies must

be present, and the LDOENA pin held low. It is assumed that DCVDD is supplied by LDO1.

ALWAYS-ON

REGISTERS

OTHER

REGISTERS

CONTROL

SEQUENCER

MEMORY

DSP FIRMWARE

MEMORY

Power-On Reset

Reset

Hardware Reset

Reset

Retained

Configurable

(see note)

Software Reset

Reset

Retained

Configurable

(see note)

Sleep Mode

Retained

Reset

Retained

Reset

Table 134 Memory Reset Summary

See “Low Power Sleep Configuration” for details of the ‘Always-On’ registers.

See “DSP Firmware Control” for details of the configurable DSP memory behaviour.

Note that, to retain the DSP firmware memory contents during Hardware Reset or Software Reset, it

must be ensured that DCVDD is held above its reset threshold. If DCVDD is powered from internal

LDO, then it is recommended to assert the LDOENA pin before the Reset, in order to maintain the

DCVDD supply.

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