WM8281ECSSLASHR datasheet(386/392 Pages) CIRRUS

386 / 392 page

WM8281

386

Rev 4.0

DIGITAL AUDIO INTERFACE CLOCKING CONFIGURATIONS

The digital audio interfaces (AIF1, AIF2, AIF3) can be configured in Master or Slave modes. In all

applications, it is important that the system clocking configuration is correctly designed. Incorrect clock

configurations will lead to audible clicks arising from dropped or repeated audio samples; this is

caused by the inherent tolerances of multiple asynchronous system clocks.

To ensure reliable clocking of the audio interface functions, it is a requirement that the external

interface clocks (eg. BCLK, LRCLK) are derived from the same clock source as SYSCLK (or

ASYNCCLK, where applicable).

In AIF Master mode, the external BCLK and LRCLK signals are generated by the WM8281 and

synchronisation of these signals with SYSCLK (or ASYNCCLK) is ensured. In this case, clocking of

the AIF is typically derived from the MCLK1 or MCLK2 inputs, either directly or via one of the

Frequency Locked Loop (FLL) circuits. It is also possible to use a different interface (AIFn or

SLIMbus) to provide the reference clock to which the AIF Master can be synchronised.

In AIF Slave mode, the external BCLK and LRCLK signals are generated by another device, as inputs

to the WM8281. In this case, it must be ensured that the applicable system clock (SYSCLK or

ASYNCCLK) is generated from a source that is synchronised to the external BCLK and LRCLK

inputs.

In a typical Slave mode application, the BCLK input is selected as the clock reference, using the FLL

to perform frequency shifting. It is also possible to use the MCLK1 or MCLK2 inputs, but only if the

selected clock is synchronised externally to the BCLK and LRCLK inputs. The SLIMbus interface can

also provide the clock reference, via one of the FLLs, provided that the BCLK and LRCLK signals are

externally synchronised with the SLIMCLK input.

The valid AIF clocking configurations are listed in Table 136 for AIF Master and AIF Slave modes.

The applicable system clock (SYSCLK or ASYNCCLK) depends on the AIFn_RATE setting for the

relevant

digital

audio

interface;

AIFn_RATE

1000,

then

SYSCLK

applicable;

AIFn_RATE

≥ 1000, then ASYNCCLK is applicable.

AIF MODE

CLOCKING CONFIGURATION

AIF Master Mode

SYSCLK_SRC (ASYNCCLK_SRC) selects MCLK1 or MCLK2 as SYSCLK

(ASYNCCLK) source.