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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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TUSB2136 Datenblatt(PDF) 47 Page - Texas Instruments |
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TUSB2136 Datenblatt(HTML) 47 Page - Texas Instruments |
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47 / 50 page  4–3 15 k Ω D+ D– DP1 DM1 15 k Ω R1 R2 5 V GND To Power Switch Figure 4–5. Downstream Connection – Only One Port Shown 4.2 Reset Timing There are two requirements for the reset signal timing. First, the reset window should be between 100 ms and 10 ms. At power up, this time is measured from the time the power ramps up to 90% of the nominal VCC until the reset signal goes high (above 1.2 V). The second requirement is that the clock has to be valid during the last 60 ms of the reset window. These two requirements are depicted in Figure 4–6. Notice that when using a 12-MHz crystal or the 48-MHz oscillator, the clock signal may take several milliseconds to ramp up and become valid after power up. Therefore, the reset window may need to be elongated up to 10 ms to ensure that there is a 60 ms overlap with a valid clock. CLK RESET t VCC 90% 3.3 V 1.2 V 0 V >60 µs 100 µs < RESET TIME < 10 ms Figure 4–6. Reset Timing |
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