P83C366BDA datasheet(13/92 Pages) PHILIPS

13 / 92 page

1999 Mar 10

Philips Semiconductors

Product speciﬁcation

Microcontrollers for PAL/SECAM TV

with OSD and VST

P8xCx66 family

TIMERS AND EVENT COUNTERS

The P8xCx66 contains two 16-bit timers/counters: Timer 0

and Timer 1 and also an 8-bit Watchdog timer.

8.1

16-bit timer/counters (T0 and T1)

Timer 0 and Timer 1 perform the following functions:

• Measure time intervals and pulse durations

• Count events

• Generate interrupt requests.

Timer 0 and Timer 1 can be independently programmed to

operate in one of four modes.

Mode 0 8-bit timer or counter with divide-by-32 prescaler.

Mode 1 16-bit time-interval or event counter.

Mode 2 8-bit time-interval or event counter with automatic

reload upon overflow.

Mode 3 Timer 0 establishes TL0 and TL1 as two

separate counters.

In the ‘timer’ function, the register is incremented every

machine cycle. Since a machine cycle consists of

12 oscillator periods, the count rate is 1

⁄12fosc.

In the ‘counter’ function, the register is incremented in

response to a HIGH-to-LOW transition. Since it takes

2 machine cycles (24 oscillator periods) to recognize a

HIGH-to-LOW transition, the maximum count rate is

⁄24fosc. To ensure that a given level is sampled, it should

be held for at least one complete machine cycle.

8.2

Watchdog timer (T3)

In addition to the standard timers, a Watchdog timer is

implemented on-chip. The Watchdog timer generates a

hardware reset upon overflow. In this way a

microcontroller system can recover from erroneous

processor states caused by electrical noise, RFI or

unexpected ROM code behaviour.

The Watchdog timer consists of an 8-bit timer with an

11-bit prescaler as shown in Fig.8. The prescaler input

frequency is 1

⁄

12fosc. The 8-bit timer is incremented every

‘t’ seconds where ‘t’ is calculated as shown below:

The 8-bit timer is an up-counter so a value 00H gives the

maximum timer interval (510 ms at 12 MHz, 1536 ms at

4 MHz), and a value of FFH gives the minimum timer

interval (2 ms at 12 MHz, 6 ms at 4 MHz). When the 8-bit

timer produces an overflow a short internal reset pulse is

generated which will reset the P8xCx66.

The timer has no disable function. Consequently, all

applications must reload the timer within the previously

loaded timer interval otherwise a reset will occur. The timer

is not stopped in the Idle mode. The interrupt routine for

the Idle mode should also service the Watchdog timer.

The Watchdog timer is controlled by the WLE bit in the

Power Control Register (see Section 9.6). The WLE bit

must be set by the Watchdog timer service routine before

the timer interval can be loaded into T3. A load of T3

automatically clears the WLE bit.

A system reset clears the Watchdog timer and the

prescaler.

8.2.1

WATCHDOG TIMER REGISTER (WDT)

Table 3

Watchdog timer Register (SFR address FFH)

76543210

T37

T36

T35

T34

T33

T32

T31

T30

2048

osc

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