ADUCM350 datasheet(17/41 Pages) AD

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ADuCM350

Data Sheet

Rev. A | Page 16 of 40

Figure 4. I2S-Compatible Interface Receiver Timing

SPI Timing

SPIH can be used for high data rate peripherals.

Table 31. SPI Master Mode Timing1

Parameter

Description

Min

Typ

Max

Unit

tSL

SCLK low pulse width2

(SPIXDIV[5:0] + 1) × tUCLK

tSH

SCLK high pulse width2

(SPIXDIV[5:0] + 1) × tUCLK

tDAV

Data output valid after SCLK edge

35.5

tDOSU

Data output setup before SCLK edge2

(SPIDIV + 1) × tUCLK

tDSU

Data input setup time before SCLK edge

58.7

tDHD

Data input hold time after SCLK edge

tDF

Data output fall time

35.5

tDR

Data output rise time

35.5

tSR

SCLK rise time

35.5

tSF

SCLK fall time

35.5

1 Guaranteed by design.

2 tUCLK = 62.5 ns. It corresponds to the maximum internal clock frequency before clock dividers.

Figure 5. SPI Master Mode Timing (Phase Mode = 1)

SCLK

AND

tSR ≥ 0.2T

VH = 2.0V

VL =0.8V

tHTR ≥ 0

tLC ≥ 0.35T

tHC ≥ 0.35T

NOTES

1. SD = SERIAL DATA, WS = WORD SELECT, WS = 0: CHANNEL 1 (LEFT), WS = 1: CHANNEL 2 (RIGHT).

SCLK

(POLARITY = 0)

1/2 SCLK

CYCLE

SCLK

(POLARITY = 1)

MOSI

MSB

BIT 6 TO BIT 1

LSB

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

tSH

tCS

tSL

3/4 SCLK

CYCLE

tSFS

tSR

tSF

tDR

tDF

tDAV

tDSU

tDHD

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