ACPL-337J datasheet(7/18 Pages) AVAGO

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Table 6. Switching Specifications (AC)

Unless otherwise noted, all typical values at TA = 25 °C, VCC1 = 5 V, VCC2 – VEE2 = 30 V, VE – VEE2 = 0 V; all Minimum/

Maximum specifications are at Recommended Operating Conditions.

Parameter

Symbol

Min.

Typ.* Max. Units Test Conditions

Fig.

Note

Input LED to High Level Output

Propagation Delay Time

tPLH

130

220

RG = 10 W, CG = 10 nF,

f = 10 kHz, Duty Cycle = 50%

13, 14,

Input LED to Low Level Output

Propagation Delay Time

tPHL

155

250

13, 14,

Pulse Width Distortion

PWD

120

3, 4

Propagation Delay Difference

Between Any 2 Parts (tPHL-tPLH)

PDD

-150

150

4, 5

Propagation Delay Skew

tPSK

100

4,6

10% to 90% Rise Time

90% to 10% Fall Time

DESAT Blanking Time

tDESAT(BLANKING)

0.6

1.1

µs

DESAT Sense to 90% VOUT Delay

tDESAT(90%)

1.3

µs

RG = 10 W, CG= 10 nF

DESAT Sense to 10% VOUT Delay

tDESAT(10%)

4.8

6.5

µs

DESAT Sense to DESAT Low

Propagation Delay

tDESAT(LOW)

0.25

µs

DESAT Sense to Low Level FAULT

Signal Delay

tDESAT(FAULT)

2.2

µs

RF = 10 kW, CF = Open

Output Mute Time due to DESAT

tDESAT(MUTE)

2.3

3.0

4.2

Time Input Kept Low Before Fault

Reset to High

tDESAT(RESET)

2.3

3.0

4.2

RF = 10 kW, CF = Open

VCC2 to UVLO High Delay

tPLH_UVLO

µs

VCC2 to UVLO Low Delay

tPHL_UVLO

µs

VCC2 UVLO to VOUT High Delay

tUVLO_ON

5.3

µs

VCC2 UVLO to VOUT Low Delay

tUVLO_OFF

µs

Output High Level Common Mode

Transient Immunity

|CMH|

>50

kV/

µs TA = 25 °C, IF = 10 mA,

VCM = 1500 V, VCC2 = 30 V

16,18,

18, 20

Output Low Level Common Mode

Transient Immunity

|CML|

>50

kV/

µs TA = 25 °C, IF = 0 mA,

VCM = 1500 V, VCC2 = 30 V,

17, 19,

19, 20

Notes:

1. tPLH is defined as propagation delay from 50% of LED input IF to 50% of High level output.

2. tPHL is defined as propagation delay from 50% of LED input IF to 50% of Low level output.

3. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.

4. As measured from IF to VOUT.

5. The difference between tPHL and tPLH between any two ACPL-337J parts under the same test conditions.

6. tPSK is equal to the worst-case difference in tPHL and tPLH that will be seen between units under the same test condition.

7. The ACPL-337J internal delay time to respond to a DESAT fault condition without any external DESAT capacitor.

8. The amount of time from when DESAT threshold is exceeded to 90% of VGATE at mentioned test conditions.

9. The amount of time from when DESAT threshold is exceeded to 10% of VGATE at mentioned test conditions.

10. The amount of time from when DESAT threshold is exceeded to DESAT Low voltage, 0.7 V.

11. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of VCC1 voltage.

12. The amount of time when DESAT threshold is exceeded, output is muted to LED input.

13. The amount of time when DESAT mute time is expired, LED input must be kept low for FAULT status to return to High.

14. The delay time when VCC2 exceeds UVLO+ threshold to UVLO high – 50% of UVLO positive-going edge.

15. The delay time when VCC2 exceeds UVLO- threshold to UVLO low – 50% of UVLO negative-going edge.

16. The delay time when VCC2 exceeds UVLO+ threshold to 50% of high level output.

17. The delay time when VCC2 exceeds UVLO- threshold to 50% of low level output.

18. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output

will remain in the high state (i.e., VOUT > 15 V or FAULT > 2 V or UVLO > 2 V). A 330 pF and a 10 kW pull-up resistor are needed in FAULT and UVLO

detection mode.

19. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output

will remain in a low state (i.e., VOUT < 1.0 V or FAULT < 0.8 V or UVLO < 0.8 V).

20. Split resistor network in the ratio 1:1 at the anode and cathode. For further details, see description of input LED driver and split resistors circuit

section in the application notes.

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