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STLC2500

3.4

Clock specifications

The STLC2500 supports, on the same input pin, the system clock both as a sine wave clock and as a dig-

ital clock (see table 15 for selection). The system clock section is powered by VDD_CLD (G08 and H09).

The voltage range for VDD_CLD is the same as for VDD_IO_A.

Table 6. System clock supported frequencies

Table 7. System clock overall specifications

Table 8. System clock, sine wave specifications

Table 9. System clock, digital clock DC specifications

Table 10. System clock, digital clock AC specifications

Table 11. Low Power clock specifications

The low power clock pin is powered by connecting VDD_IO_B to the wanted supply.

Symbol

Parameter

Values

Unit

Clock input frequency list

13, 26, 19.2, 38.4

MHz

Symbol

Parameter

Min.

Typ.

Max.

Unit

Tolerance on input frequency

-20

20

ppm

Symbol

Parameter

Min.

Typ.

Max.

Unit

Peak to peak voltage range

0.2

0.5

1

V

Total harmonic content of input signal

-25

dBc

Real part of parallel input impedance at pin

30

60

90

K

Ω

Symbol

Parameter

Min.

Typ.

Max.

Unit

Low Level input voltage

0.22 *

VDD_IO_A

V

High Level input voltage

0.85 *

VDD_IO_A

V

Symbol

Parameter

Min.

Typ.

Max.

Unit

10%-90% rise time

1,5

6

ns

90%-10% fall time

1,5

6

ns

Duty Cycle

45

50

55

%

Symbol

Parameter

Min.

Typ.

Max.

Unit

Duty Cycle

30

70

%

Accuracy

±250

ppm