© VITESSE SEMICONDUCTOR CORPORATION

Page 7

8/28/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC6048

G52335-0, Rev. 4.0

High-Speed Octal

Programmable Timing Generator

Table 8: AC Characteristics

NOTE: (1) The rising edge of the input (INA, INB) must fall in the setup region defined from 250ps to 1250ps before the rising

edge of the reference clock (RCK, RCKN).

Parameter

Description

Min

Typ

Max

Units

INA and INB Reprogram Rate

5

ns

TSET Reprogram Rate, 200MHz Application

5

ns

TSET Reprogram Rate, 100MHz Application

10

ns

10

ps

Propagation Delay, 200MHz Application

Full TG Span (TSET = 0011111111)

After Vernier Span DAC Calibration

4980

4990

ps

Propagation Delay, 100MHz Application

Full TG Span (TSET = 1111111111)

After Vernier Span DAC Calibration

9980

9990

ps

Propagation Delay

Vernier Delay Element Span (TSET=0001111111)

After Vernier Span DAC Calibration

1230

1240

ps

Propagation Delay

TG Minimum Delay (TSET=000000000)

11.0

14.0

ns

Propagation Delay

Vernier Delay Element Zero Delay

1300

1700

ps

INL

Integral Non-Linearity

Dynamic on-the-fly TSET Switching

-4

+4

LSBs

DNL

Differential Non-Linearity

Dynamic on-the-fly TSET Switching

-4

+4

LSBs

DCV

Variation in Delay vs. Duty Cycle and Frequency

Full TG Span (TSET=1111111111)

-40

+40

ps

Variation in Delay vs. Temperature

Full TG Span (TSET=1111111111)

-6

+6

ps/

°C

PSRR

Variation in Delay vs. Supply Voltage

Full TG Span (TSET=1111111111)

-8

+8

ps/100mV

OSJ

Random Output Signal Jitter

10

ps rms

Calibration DAC Resolution

25

ps

Width of the Output Pulse

800

2500

ps

Output Rise/Fall Times (20% to 80%)

300

ps

250

1250

ps

1750

ps

TSET [0:9] Setup with Respect to IN

250

ps

TSET [0:9] Hold with Respect to IN

3500

ps

IN0 - IN7 Pulse Width

2

ns