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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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IOBUS0 Datenblatt(PDF) 47 Page - Future Technology Devices International Ltd. |
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IOBUS0 Datenblatt(HTML) 47 Page - Future Technology Devices International Ltd. |
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47 / 88 page  47 C opyright © Future T ec hnology Devic es I nternational Limited Datasheet Vinculum-II Embedded Dual USB Host Controller IC V ers ion 1 .7 Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43 6.3.5 Unmanaged Mode The VNC2 SPI Slave also supports an unmanaged SPI mode. This is a simple data exchange between Master and Slave. It operates in the standard 4 pin mode (SS#, CLK, MOSI and MISO) with all transfers controlled by the SPI Master. When the CPU wants to send data out of the SPI Slave it writes this into the spi_slave_data_tx register. This will then be moved into the transfer shift register to wait for the SPI Master to request it. The SPI Master will at some point assert SS# and start clocking data on MOSI with SCK. As this is shifted into the transfer shift register, the SPI Slave will also be shifting data in the opposite direction on MISO. At the end of the transfer the SPI Slave copies the received data from the shift register to spi_slave_data_rx as seen in Figure 6.12. SPI Clk Div 0 1 2 3 4 5 6 7 Rx Shift Register SPI Master SPI Slave ss# clk mosi miso 0 1 2 3 4 5 6 7 Shift Register 0 1 2 3 4 5 6 7 Shift Register 0 1 2 3 4 5 6 7 Tx Shift Register Figure 6.12 Unmanaged Mode Transfer Diagram |
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