IOBUS1 datasheet(40/88 Pages) FTDI

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

V ers ion 1 .7

Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43

Mode

Pins

Word Size

Handshaking

Speed

Comments

VNC1L

Yes

Read 66%

Write 66%

Legacy mode

Full Duplex

Yes

Read 50%

Write 100%

Half Duplex 4 pin

Yes

Read 100%

Write 100%

MOSI becomes

bi-directional

Half Duplex 3 pin

Yes

Read 50%

Write 50%

MOSI becomes

bi-directional

Unmanaged

Read 100%

Write 100%

Table 6.3 - SPI Slave Speeds

VNC2 SPI Master is described in Section 6.4.1 SPI Master Signal Descriptions.

Table 6.5 shows the SPI master signals and the available pins that they can be mapped to depending on

the package size. Further details on the configuration of input and output signals are available in Section

5 - I/O Multiplexer.

6.2.1 SPI Clock Phase Modes

SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known

as Mode 0, Mode 1, Mode 2 and Mode 3. Table 6.4 summarizes these modes and available interface and

Figure 6.3 is the function timing diagram.

For CPOL = 0, the base (inactive) level of SCLK is 0.

In this mode:



When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on the

falling edge of SCLK.



When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on the

rising edge of SCLK

For CPOL =1, the base (inactive) level of SCLK is 1.

In this mode:



When CPHA = 0, data v in on the falling edge of SCLK, and data is clocked out on the rising edge

of SCLK



When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on the

falling edge of SCLK.

Mode

CPOL

CPHA

Full

Duplex

Half

Duplex

4 pin

Half

Duplex

3 pin

Unmanaged

VNC1L

Legacy

Table 6.4 - Clock Phase/Polarity Modes

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