ADC10831CIWM datasheet(6/30 Pages) NSC

6 / 30 page

Electrical Characteristics (Continued)

The following specifications apply for Va e AVa e DVa ea50 VDC VREFa ea4096 VDC VREFb e VIN e GND

Vb eb50 VDC and fCLK e 25 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX

all other limits TA e TJ ea25 C (Note 16)

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 11)

(Note 12)

(Limits)

AC CHARACTERISTICS

fCLK

Clock Frequency

MHz(max)

kHz(min)

Clock Duty Cycle

%(min)

%(max)

Conversion Time

Clock

Cycles

s(max)

Acquisition Time

Clock

Cycles

s(max)

tSCS

CS Set-Up Time Set-Up Time from Falling Edge of

ns(min)

CS to Rising Edge of Clock

(1 tCLK

(max)

14 ns)

30 ns)

tSDI

DI Set-Up Time Set-Up Time from Data Valid on

ns(min)

DI to Rising Edge of Clock

tHDI

DI Hold Time Hold Time of DI Data from Rising

ns(min)

Edge of Clock to Data not Valid on DI

tAT

DO Access Time from Rising Edge of CLK When

ns(min)

CS is ‘‘Low’’ during a Conversion

tAC

DO or SARS Access Time from CS Delay from

ns(max)

Falling Edge of CS to Data Valid on DO or SARS

tDSARS

Delay from Rising Edge of Clock to Falling Edge of

100

200

ns(max)

SARS when CS is ‘‘Low’’

tHDO

DO Hold Time Hold Time of Data on DO after

ns(max)

Falling Edge of Clock

tAD

DO Access Time from Clock Delay from Falling

ns(max)

Edge of Clock to Valid Data of DO

t1H t0H

Delay from Rising Edge of CS to DO or SARS

ns(max)

TRI-STATE

tDCS

Delay from Falling Edge of Clock to Falling Edge of

ns(min)

tCS(H)

CS ‘‘HIGH’’ Time for AD Reset after Reading of

1 CLK

cycle(min)

Conversion Result

tCS(L)

ADC10731 Minimum CS ‘‘Low’’ Time to Start a

1 CLK

cycle(min)

Conversion

tSC

Time from End of Conversion to CS Going ‘‘Low’’

5 CLK

cycle(min)

tPD

Delay from Power-Down command to 10% of

Operating Current

tPC

Delay from Power-Up Command to Ready to Start

a New Conversion

CIN

Capacitance of Logic Inputs

COUT

Capacitance of Logic Outputs

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