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OMAP3530ECUS72 Datenblatt(PDF) 66 Page - Texas Instruments

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Teilenummer OMAP3530ECUS72
Bauteilbeschribung  Applications Processors
PDF  265 Pages
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

OMAP3530ECUS72 Datenblatt(HTML) 66 Page - Texas Instruments

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
AF9
NA
etk_d14
0
O
L
L
4
vdds
Yes
4
(21)
PU100/
LVCMOS
PD100
hsusb2_data
3
IO
0
gpio_28
4
IO
mm2_rxrcv
5
IO
hsusb2_tll_d
6
IO
ata0
hw_dbg16
7
O
AE9
NA
etk_d15
0
O
L
L
4
vdds
Yes
4
(21)
PU100/
LVCMOS
PD100
hsusb2_data
3
IO
1
gpio_29
4
IO
mm2_txse0
5
IO
hsusb2_tll_d
6
IO
ata1
hw_dbg17
7
O
Y15
NA
jtag_emu0
0
IO
H
H
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_11
4
IO
safe_mode
7
-
Y14
NA
jtag_emu1
0
IO
H
H
0
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_31
4
IO
safe_mode
7
-
U3
NA
mcbsp3_clkx
0
IO
L
L
7
vdds
Yes
4
(22)
PU100/
LVCMOS
PD100
uart2_tx
1
O
gpio_142
4
IO
hsusb3_tll_d
5
IO
ata6
safe_mode
7
-
N3
NA
mcbsp3_dr
0
I
L
L
7
vdds
Yes
4
(22)
PU100/
LVCMOS
PD100
uart2_rts
1
O
gpio_141
4
IO
hsusb3_tll_d
5
IO
ata5
safe_mode
7
-
P3
NA
mcbsp3_dx
0
IO
L
L
7
vdds
Yes
4
(22)
PU100/
LVCMOS
PD100
uart2_cts
1
I
gpio_140
4
IO
hsusb3_tll_d
5
IO
ata4
safe_mode
7
-
W3
NA
mcbsp3_fsx
0
IO
L
L
7
vdds
Yes
4
(22)
PU100/
LVCMOS
PD100
uart2_rx
1
I
gpio_143
4
IO
hsusb3_tll_d
5
IO
ata7
safe_mode
7
-
V3
NA
mcbsp4_clkx
0
IO
L
L
7
vdds
Yes
4
(22)
PU100/
LVCMOS
PD100
gpio_152
4
IO
hsusb3_tll_d
5
IO
ata1
mm3_txse0
6
IO
(22) The capacity load range is [2 pf to 6 pF].
66
TERMINAL DESCRIPTION
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