80

Registers

The system programmer may access any of the UART reg-

isters summarized in Table II via the CPU These registers

control UART operations including transmission and recep-

tion of data Each register bit in Table II has its name and

reset state shown

81

LINE CONTROL REGISTER

The system programmer specifies the format of the asyn-

chronous data communications exchange and set the Divi-

sor Latch Access bit via the Line Control Register (LCR)

The programmer can also read the contents of the Line

Control Register The read capability simplifies system pro-

gramming and eliminates the need for separate storage in

system memory of the line characteristics Table II shows

the contents of the LCR Details on each bit follow

Bits 0 and 1

These two bits specify the number of bits in

each transmitted or received serial character The encoding

of bits 0 and 1 is as follows

Bit 1

Bit 0

Character Length

0

0

5 Bits

0

1

6 Bits

1

0

7 Bits

1

1

8 Bits

Bit 2

This bit specifies the number of Stop bits transmitted

and received in each serial character If bit 2 is a logic 0

one Stop bit is generated in the transmitted data If bit 2 is a

logic 1 when a 5-bit word length is selected via bits 0 and 1

one and a half Stop bits are generated If bit 2 is a logic 1

when either a 6- 7- or 8-bit word length is selected two

Stop bits are generated The Receiver checks the first Stop-

bit only regardless of the number of Stop bits selected

Bit 3

This bit is the Parity Enable bit When bit 3 is a logic 1

a Parity bit is generated (transmit data) or checked (receive

data) between the last data word bit and Stop bit of the

serial data (The Parity bit is used to produce an even or odd

number of 1s when the data word bits and the Parity bit are

summed)

Bit 4

This bit is the Even Parity Select bit When bit 3 is a

logic 1 and bit 4 is a logic 0 an odd number of logic 1s is

transmitted or checked in the data word bits and Parity bit

When bit 3 is a logic 1 and bit 4 is a logic 1 an even number

of logic 1s is transmitted or checked

Bit 5

This bit is the Stick Parity bit When bits 3 4 and 5 are

logic 1 the Parity bit is transmitted and checked as a logic 0

If bits 3 and 5 are 1 and bit 4 is a logic 0 then the Parity bit is

transmitted and checked as a logic 1 If bit 5 is a logic 0

Stick Parity is disabled

Bit 6

This bit is the Break Control bit It causes a break

condition to be transmitted to the receiving UART When it

is set to a logic 1 the serial output (SOUT) is forced to the

Spacing (logic 0) state The break is disabled by setting bit 6

to a logic 0 The Break Control bit acts only on SOUT and

has no effect on the transmitter logic

Note

This feature enables the CPU to alert a terminal in a computer com-

munications system If the following sequence is followed no errone-

ous or extraneous characters will be transmitted because of the

break

1 Load an all 0s pad character in response to THRE

2 Set break after the next THRE

normal transmission has to be restored

During the break the Transmitter can be used as a character timer to accu-

rately establish the break duration

TABLE III Baud Rates Divisors and Crystals

18432 MHz Cystal

3072 MHz Crystal

18432 MHz Crystal

Baud Rate

Decimal Divisor

Percent Error

Decimal Divisor

Percent Error

Decimal Divisor

Percent Error

50

2304

3840

23040

75

1536

2560

15360

110

1047

0026

1745

0026

10473

1345

857

0058

1428

0034

8565

150

768

1280

7680

300

384

640

3840

600

192

320

1920

1200

96

160

920

1800

64

107

0312

640

2000

58

069

96

576

2400

48

80

480

3600

32

53

0628

320

4800

24

40

240

7200

16

27

123

160

9600

12

20

120

19200

6

10

60

38400

3

5

30

56000

2

286

21

204

128000

9

Note

For baud rates of 250k 300k 375k 500k 750k and 15M using a 24 MHz crystal causes minimal error

15