PC87351 datasheet(48/86 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.12.5

GPIO Pin Configuration Access Register

This register reflects, for both read and write, the register currently selected by the GPIO Pin Configuration Select Register.

All the configuration registers that are accessed via this register have a common bit structure, as shown below. This register

is reset by hardware to 44h.

Location:

Index F1h

Type:

R/W

Bit

76543210

Name

Reserved

IRQ

Debounce

Enable

IRQ Polarity IRQ Type

Lock

Pull-Up

Control

Output

Type

Output

Enable

Reset

01000100

Bit

Description

Reserved

IRQ Debounce Enable

0: Disabled

1: Enabled (default)

IRQ Polarity. This bit deﬁnes the polarity of the signal that issues an interrupt from the corresponding GPIO pin

(falling/low or rising/high).

0: Falling edge or low level input (default)

1: Rising edge or high level input

IRQ Type. This bit deﬁnes the signal type that issues an interrupt from the corresponding GPIO pin.

0: Edge input (default)

1: Level input

Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to

0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O

Conﬁguration 3 Register, SIOCF3).

0: No effect (default)

1: Direction, output type, pull-up and output value locked

Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.

It supports open-drain output signals with internal pull-ups and TTL input signals

0: Disabled

1: Enabled (default)

Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.

0: Open-drain (default)

1: Push-pull

Output Enable. This bit indicates the GPIO pin output state. It has no effect on input.

0: TRI-STATE (default)

1: Output enabled

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