L6718 datasheet(43/71 Pages) STMICROELECTRONICS

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L6718

L6718 power manager

7.1.1

SMBus sequence

The bus master sends the start (START) sequence followed by 7 bits which identify the

controller address. The bus master then sends READ/WRITE and the controller then sends

the acknowledge (ACK) bit.

The bus master sends the command code during the command phase. The controller sends

the acknowledge bit after the command phase.

If a READ command is sent by the master, the device drives the SDA wire in order to reply

to the master request with DATA BYTE or DATA WORD (2 bytes) depending on the

command. The controller sends the acknowledge (ACK) bit after the data stream. Finally,

the bus master sends the stop (STOP) sequence.

WRITE command: The master sends the data stream related to the command phase

previously issued (if applicable). The controller achieves the data stream by the masters

and sends the acknowledge (ACK). Finally the bus master sends the stop (STOP)

sequence.

After the controller has detected the STOP sequence, it performs operations according to

the command issued by the master.

Figure 8. SMBus communication format

7.2

SMBus tables

SCL

START

ACK

Addressing Phase

(7 Clocks)

R/W

(1Ck)

ACK

(1Ck)

Command Phase

(8 Clocks)

STOP

START

SLAVE ADDRESSING + R/W

COMMAND PHASE

ACK

STOP

BUS DRIVEN BY L6718 (SL AVE)

BUS DRIVEN BY MASTER

654

ACK

DATA PHASE

Data Phase

(8 Clocks)

ACK

(1Ck)

ACK

(1Ck)

SDA

AM12882v1

Table 14. SMBus addressing

Mode

VRM address

Address

domain

SMBus

multi-phase

SMBus

single-phase

CPU mode

00h

CCh

8Ch

CPU mode

01h

CEh

8Eh

DDR mode

02h (06h in DDR4)

E0h

E2h (Jmode only)

DDR mode

02h (06h in DDR4)

E8h

EAh (Jmode only)

DDR mode

04h (08h in DDR4)

E4h

E6h (Jmode only)

DDR mode

04h (08h in DDR4)

ECh

EEh (Jmode only)

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