ST7MC1K2-Auto datasheet(48/371 Pages) STMICROELECTRONICS

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6.5

System integrity management (SI)

The system integrity management block contains the low voltage detector (LVD), auxiliary

voltage detector (AVD) and clock security system (CSS) functions. It is managed by the

SICSR register.

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 11.2.2 on page 309 for further details.

6.5.1

Low voltage detector (LVD)

The low voltage detector function (LVD) generates a static reset when the VDD supply

voltage is below a VIT- reference value. This means that it secures the power-up as well as

the power-down keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-

on in order to avoid a parasitic reset when the MCU starts running and sinks current on the

supply (hysteresis).

The LVD reset circuitry generates a reset when VDD is below:

●

VIT+ when VDD is rising

●

VIT- when VDD is falling

The LVD function is illustrated in Figure 13.

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the

MCU can only be in two modes:

●

under full software control

●

in static safe reset

In these conditions, secure operation is always ensured for the application without the need

for external reset hardware.

During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to

reset other devices.

Note:

The LVD allows the device to be used without any external reset circuitry.

The LVD is an optional function which can be selected by option byte.

It is recommended to make sure that the VDD supply voltage rises monotonously when the

device is exiting from reset, to ensure the application functions properly.

Figure 13.

Low voltage detector vs reset

VDD

VIT+

Reset

VIT-

Vhys

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