ST72345C4 datasheet(84/247 Pages) STMICROELECTRONICS

84 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

84/247

Doc ID 12321 Rev 6

Note:

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is

cleared).

●

Watchdog reset on Halt option

If the watchdog is activated and the watchdog reset on halt option is selected, then the

HALT instruction will generate a Reset.

11.1.4

Using Halt mode with the WDG

If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT

instruction), it is recommended before executing the HALT instruction to refresh the WDG

counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

11.1.5

How to program the watchdog timeout

Figure 38 shows the linear relationship between the 6-bit value to be loaded in the watchdog

counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a

quick calculation without taking the timing variations into account. If more precision is

needed, use the formulae in Figure 39.

Caution:

When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 38.

Approximate timeout duration

Watchdog timeout (ms) @ 8 MHz fOSC2

128

1.5

114

ST72345C4 Datenblatt(PDF) 84 Page - STMicroelectronics