STM32L432KB datasheet(122/149 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32L432KB STM3L432KC

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DocID028798 Rev 2

6.3.18

Digital-to-Analog converter characteristics

Table 67. DAC characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Analog supply voltage for

DAC ON

1.8

3.6

VREF+

Positive reference voltage

1.8

VDDA

VREF-

Negative reference

voltage

-VSSA

Resistive load

DAC output

buffer ON

connected to VSSA

kΩ

connected to VDDA

Output Impedance

DAC output buffer OFF

9.6

11.7

13.8

kΩ

RBON

Output impedance sample

and hold mode, output

buffer ON

VDD = 2.7 V

kΩ

VDD = 2.0 V

3.5

RBOFF

Output impedance sample

and hold mode, output

buffer OFF

VDD = 2.7 V

16.5

kΩ

VDD = 2.0 V

18.0

Capacitive load

DAC output buffer ON

CSH

Sample and hold mode

0.1

µF

VDAC_OUT

Voltage on DAC_OUT

output

DAC output buffer ON

0.2

VREF+

– 0.2

DAC output buffer OFF

VREF+

tSETTLING

Settling time (full scale: for

a 12-bit code transition

between the lowest and

the highest input codes

when DAC_OUT reaches

final value ±0.5LSB,

±1 LSB, ±2 LSB, ±4 LSB,

±8 LSB)

Normal mode

DAC output

buffer ON

CL ≤ 50 pF,

RL ≥ 5 kΩ

±0.5 LSB

1.7

µs

±1 LSB

1.6

2.9

±2 LSB

1.55

2.85

±4 LSB

1.48

2.8

±8 LSB

1.4

2.75

Normal mode DAC output buffer

OFF, ±1LSB, CL = 10 pF

-2

2.5

tWAKEUP(2)

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until

final value ±1 LSB

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

-4.2

7.5

µs

Normal mode DAC output buffer

OFF, CL ≤ 10 pF

-2

PSRR

VDDA supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 kΩ, DC

--80

-28

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