TABLE 6. Time-Slot and Port Assignment Instruction

Bit Number and Name

Function

7

6

5

43210

EN

PS

T

5

T

4

T

3

T

2

T

1

T

0

(Note 6)

(Note 7)

0

1

X

XXXXX

Disable D

Disable D

1

1

Assign One Binary Coded Time-Slot from 0–63

Enable D

Assign One Binary Coded Time-Slot from 0–63

Enable D

Note 6: The “PS” bit MUST be set to “1” for both transmit and receive for the TP3076.

Note 7: T5 is the MSB of the time-slot assignment bit field. Time-slot bits should be set to “000000” for both transmit and receive when operating in non-delayed data

timing mode.

TIME-SLOT ASSIGNMENT

COMBO II can operate in either fixed time-slot or time-slot

assignment mode for selecting the Transmit and Receive

PCM time-slots. Following power-on, the device is automati-

cally in Non-Delayed Timing mode, in which the time-slot al-

ways begins with the leading (rising) edge of frame sync in-

puts FS

with Delay Data timing; see

Figure 4.FS

have any phase relationship with each other in BCLK period

increments.

Alternatively, the internal time-slot assignment counters and

comparators can be used to access any time-slot in a frame,

using the frame sync inputs as marker pulses for the begin-

ning of transmit and receive time-slot 0. In this mode, a

frame may consist of up to 64 time-slots of 8 bits each. A

time-slot is assigned by a 2-byte instruction as shown in

Table 1 and Table 6. The last 6 bits of the second byte indi-

cate the selected time-slot from 0–63 using straight binary

notation. When writing a time-slot and port assignment reg-

ister, if the PCM interface is currently active, it is immediately

deactivated to prevent possible bus clashes. A new assign-

ment becomes active on the second frame following the end

of the Chip-Select for the second control byte. Rewriting of

the register contents should not be performed during the

talking period of a connection to prevent waveform distortion

caused by loss of a sample which will occur with each regis-

ter write. The “EN” bit allows the PCM input, D

D

Time-Slot Assignment mode requires that the FS

pulses conform to the delayed data timing format shown in

Figure 4.

PORT SELECTION

On the TP3076, the “PS” bit MUST always be set to 1.

Table 6 shows the format for the second byte of both trans-

mit and receive time-slot and port assignment instructions.

TRANSMIT GAIN INSTRUCTION BYTE 2

The transmit gain can be programmed in 0.1 dB steps by

writing to the Transmit Gain Register as defined in

Table 1

and

Table 7. This corresponds to a range of 0 dBm0 levels at

VF

+5.0 dBm to −20.4 dBm in 600

Ω).

To calculate the binary code for byte 2 of this instruction for

any desired input 0 dBm0 level in Vrms, take the nearest in-

teger to the decimal number given by:

200 x log

and convert to the binary equivalent. Some examples are

given in

Table 7. A complete tabulation is given in Appendix

I of AN-614.

It should be noted that the Transmit (idle channel) Noise and

Transmit Signal to Total Distortion are both specified with

transmit gain set to 0 dB (gain register set to all ones). At

high transmit gains there will be some degradation in noise

performance for these parameters. See Application Note

AN-614 for more information on this subject.

TABLE 7. Byte 2 of Transmit Gain Instruction

Bit Number

0 dBm0 Test Level (Vrms)

76543210

at VF

00000000

No Output (Note 8)

00000001

0.074

00000010

0.075

——

11111110

1.359

11111111

1.375

codes representing idle noise.

RECEIVE GAIN INSTRUCTION BYTE 2

The receive gain can be programmed in 0.1 dB steps by writ-

ing to the Receive Gain Register as defined in

Table 1 and

Table 8. Note the following restrictions on output drive capa-

bility:

1.

0 dBm0 levels

≤ 1.96 Vrms at VF

a load of

≥ 15 kΩ to GND; Receive Gain set to 0 dB (gain

register set to all ones).

2.

0 dBm0 levels

≤ 1.85 Vrms at VF

a load of

≥ 600Ω to GND; Receive Gain set to 0.5 dB.

3.

0 dBm0 levels

≤ 1.71 Vrms at VF

a load of

≥ 300 Ω to GND. Receive Gain set to −1.2 dB.

To calculate the binary code for byte 2 of this instruction for

any desired output 0 dBm0 level in Vrms, take the nearest in-

teger to the decimal number given by:

200 x log

and convert to the binary equivalent. Some examples are

given in

Table 8. A complete tabulation is given in Appendix I

or AN-614.

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