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TPS53353 Datenblatt(PDF) 17 Page - Texas Instruments |
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TPS53353 Datenblatt(HTML) 17 Page - Texas Instruments |
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17 / 37 page ![]() = £ p ´ ´ SW 0 OUT f 1 f 2 ESR C 4 ( ) = ´ ´ OUT 1 H s s ESR C R1 R2 Voltage Divider 1 + VFB + 0.6 V PWM Control Logic and Divider L ESR COUT VC RLOAD IIND IOUT UDG-11193 IC Switching Modulator Output Capacitor VOUT TPS53353 VIN VIN LL 17 TPS53353 www.ti.com SLUSAK2C – AUGUST 2011 – REVISED FEBRUARY 2016 Product Folder Links: TPS53353 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The output voltage decreases. If the output voltage reaches UV threshold, then both high-side MOSFET and low-side MOSFET driver will be OFF and the device restarts after a hiccup delay. If the OV condition remains, both high- side MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed. 7.3.8 UVLO Protection The TPS53353 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than 3.95 V, the device shuts off. When the VREG voltage is higher than 4.2V, the device restarts. This is a non-latch protection. 7.3.9 Thermal Shutdown TPS53353 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 145°C), TPS53353 is shut off. When the temperature falls about 10°C below the threshold value, the device will turn back on. This is a non-latch protection. 7.4 Device Functional Modes 7.4.1 Small Signal Model From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 37. Figure 37. Simplified Modulator Model The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity). The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially constant. (5) For loop stability, the 0-dB frequency, ƒ0, defined in Equation 6 needs to be lower than 1/4 of the switching frequency. (6) |
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