ST8034HN datasheet(21/31 Pages) STMICROELECTRONICS

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ST8034HN, ST8034HC

Functional description

Figure 8. External clock usage

The clock frequency is selected by the CLKDIV1 and CLKDIV2 pins and is fXTAL, fXTAL/2,

fXTAL/4 or fXTAL/8 in the case of the ST8034HN or either fXTAL or fXTAL/2 in the case of the

ST8034HC, selected by the CLKDIV pin, see Table 12.

The frequency change is synchronous, meaning that after transition on the CLKDIV input,

the present clock period is completed and after that the new whole clock period starts,

therefore no clock period is shortened during the frequency switchover.

If an external crystal is used, the duty cycle on the CLK pin should be between 45% and

55%. If an external clock is connected to the XTAL1 pin, its duty cycle must be between 48%

and 52% so that the CLK output duty cycle is between 45% and 55%.

6.4

Input and output circuits

When the I/O and I/OUC pins are pulled high by a 9 k

 resistor between I/O and VCC and/or

10 k

 resistor between I/OUC and VDD(INTF), both lines enter the idle state. The I/O pin is

referenced to VCC and the I/OUC pin to VDD(INTF), which allows operation at VCC level

different from VDD(INTF) level.

Table 12. Clock frequency selection

ST8034HN

CLKDIV1 pin level

CLKDIV2 pin level

CLK frequency

Low

fXTAL/8

Low

High

fXTAL/4

High

fXTAL/2

High

Low

fXTAL

ST8034HC

CLKDIV pin level

CLK frequency

High

fXTAL/2

Low

fXTAL

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