7

converters for 5V Main and 3.3V Main buses, two linear

regulators for 3.3V ALWAYS and 5V ALWAYS, and a 12V

boost converter.

The two synchronous converters operate out of phase to

substantially reduce the input-current ripple, minimizing input

filter requirements, minimizing battery heating and

prolonging battery life.

The 12V boost controller uses a 100kHz clock derived from

the main clock. This controller uses leading edge modulation

with the maximum duty cycle limited to 33%.

The chip has three input control lines SDWN1, SDWN2 and

SDWNALL. These are provided for Advanced Configuration

and Power Interface (ACPI) compatibility. They turn on and

off all outputs, as well as provide independent control of the

3.3V Main and +5V Main outputs.

To maximize efficiency for the 5V Main and 3.3V Main outputs,

the current-sense technique is based on the lower MOSFET

hysteretic mode of operation which is automatically engaged at

light loads when the inductor current becomes discontinuous.

3.3V Main and 5V Main Architecture

These main outputs are generated from the unregulated

battery input by two independent synchronous buck

converters. The IC integrates all the components required

for output voltage setpoint and feedback compensation,

significantly reducing the number of external components,

saving board space and parts cost.

The buck PWM controllers employ a 300kHz fixed frequency

current-mode control scheme with input voltage feed-

forward ramp programming for better rejection of input

voltage variations.

Figure 4 shows the out-of-phase operation for the 3.3V Main

and 5V Main outputs. The phase node is the junction of the

upper MOSFET, lower MOSFET and the output inductor.

The phase node is high when the upper MOSFET is

conducting and the inductor current rises accordingly. When

the phase node is low, the lower MOSFET is conducting and

the inductor current is ramping down as shown.

Current Sensing and Current Limit Protection

Both PWM converters use the lower MOSFET on-state

technique eliminates the need for a current sense resistor

and the associated power losses. If more accurate current

protection is desired, current sense resistors may be used in

series with the lower MOSFETs’ source.

To set the current limit, place a resistor, RSNS, between the

ISEN inputs and the drain of the lower MOSFET (or optional

current sense resistor). The required value of the RSNS

resistor is determined from the following equation:

where IOCDC is the desired DC overcurrent limit; RCS is

optional current-sense resistor, Vo is the output voltage and L

is the output inductor. Also, the value of RCS should be

specified for the expected maximum operating

temperature.

The sensed voltage, and the resulting current out of the

ISEN pin through RSNS, is used for current feedback and

current limit protection. This is compared with an internal

current limit threshold. When a sampled value of the output

current is determined to be above the current limit

threshold, the PWM drive is terminated and a counter is

initiated. This limits the inductor current build-up and

essentially switches the converter into current-limit mode. If

an overcurrent is detected between 26

µs to 53µs later, an

overcurrent shutdown is initiated. If during the 26

µs to 53µs

period, an overcurrent is not detected, the counter is reset

and sampling continues as normal.

This current limit scheme has proven to be very robust in

applications like portable computers where fast inductor

current build-up is common due to a large difference

between input and output voltages and a low value of the

inductor.

Light-Load (Hysteretic) Operation

In the light-load (hysteretic) mode the output voltage is

regulated by the hysteretic comparator which regulates the

output voltage by maintaining the output voltage ripple as

shown in Figure 5. In Hysteretic mode, the inductor current

flows only when the output voltage reaches the lower limit of

the hysteretic comparator and turns off at the upper limit.

Hysteretic mode saves converter energy at light loads by

supplying energy only at the time when the output voltage

requires it. This mode conserves energy by reducing the

power dissipation associated with continuous switching.

RSNS

Rcs

135

µA

------------------ Iocdc

Vo

L2

300kHz

×

×

-----------------------------------------

+





100

–

=

0 A, V

0 A, V

5V PHASE (10V/DIV.)

1

µs/DIV.

5A

5A

3.3V PHASE (10V/DIV.)

FIGURE 4. OUT OF PHASE OPERATION

IPM6220