W78ERD2 datasheet(7/76 Pages) ETC2

7 / 76 page

W78ERD2/W78ERD2A

Publication Release Date: March 2, 2009

- 7 -

Revision A12

Timer 2 is controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an

external event counter or an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has

three operating modes: capture, auto-reload, and baud rate generator. In capture or auto-reload mode,

RCAP2H and RCAP2L are the reload / capture registers and the clock speed is the same as that of

Timers 0 and 1.

5.3

Clock

The W78ERD2 is designed for either a crystal oscillator or an external clock.

The W78ERD2 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be

connected across pins XTAL1 and XTAL2, and a load capacitor may be connected from each pin to

ground. In addition, if the crystal frequency is higher than 24 MHz, a resistor should be connected

between XTAL1 and XTAL2 to provide a DC bias.

An external clock is connected to pin XTAL1, while pin XTAL2 should be left disconnected. The XTAL1

input is a CMOS-type input, as required by the crystal oscillator. As a result, the logic-1 voltage should

be higher than 3.5 V.

5.4

Power Management

The W78ERD2 provides two modes, idle mode and power-down mode, to reduce power consumption.

Both modes are entered by software.

The W78ERD2 enters Idle mode when the IDL bit in the PCON register is set. In Idle mode, the

internal clock for the processor stops while the internal clock for the peripherals and interrupt logic

continues to run. The W78ERD2 leaves Idle mode when an interrupt or a reset occurs.

The W78ERD2 enters Power-Down mode when the PD bit in the PCON register is set. In Power-Down

mode, all of the clocks are stopped, including the oscillator. The W78ERD2 leaves Power-Down mode

when there is a hardware reset or by external interrupts

INT0 or INT1, if enabled.

5.5

Reduce EMI Emission

If the crystal frequency is less than 25 MHz, set bit 7 in the option register to 0 to reduce EMI

emissions. Please see Option Bits for more information.

5.6

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running, as the W78ERD2 has a special glitch-removal circuit

that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, and all of the other SFR to 00H,

with two exceptions—SBUF does not change, and bit 4 in PCON is not cleared.

W78ERD2 Datenblatt(PDF) 7 Page - List of Unclassifed Manufacturers