DOC4106 datasheet(6/47 Pages) ATMEL

6 / 47 page

AT8xC51SND1C

4106F–8051–10/02

Timer 0 External Clock Input

When Timer 0 operates as a counter, a falling edge on the T0 pin

increments the count.

P3.4

Timer 1 External Clock Input

When Timer 1 operates as a counter, a falling edge on the T1 pin

increments the count.

P3.5

Table 4. Audio Interface Signal Description

Signal

Name

Type

Description

Alternate

Function

DCLK

DAC Data Bit Clock

DOUT

DAC Audio Data

DSEL

DAC Channel Select Signal

DSEL is the sample rate clock output.

SCLK

DAC System Clock

SCLK is the oversampling clock synchronized to the digital audio data

(DOUT) and the channel selection signal (DSEL).

Table 5. USB Controller Signal Description

Signal

Name

Type

Description

Alternate

Function

D+

I/O

USB Positive Data Upstream Port

This pin requires an external 1.5 k

Ω pull-up to VDD for full speed

operation.

D-

I/O

USB Negative Data Upstream Port

Table 6. MutiMediaCard Interface Signal Description

Signal

Name

Type

Description

Alternate

Function

MCLK

MMC Clock output

Data or command clock transfer.

MCMD

I/O

MMC Command line

bi-directional command channel used for card initialization and data

transfer commands. To avoid any parasitic current consumption,

unused MCMD input must be polarized to

DD or VSS.

MDAT

I/O

MMC Data line

bi-directional data channel. To avoid any parasitic current consumption,

unused MDAT input must be polarized to

VDD or VSS.

Table 3. Timer 0 and Timer 1 Signal Description (Continued)

Signal

Name

Type

Description

Alternate

Function

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