AS2845D-8 datasheet(20/20 Pages) ETC

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AS2842/3/4/5

Current Mode Controller

ASTEC Semiconductor

operating under very light load can experience

instabilities caused by the low amplitude of the

current sense ramp waveform. In such a case,

any noise on the waveform can be sufficient to

trip the comparator resulting in random and pre-

mature pulse termination. The addition of a small

amount of artificial ramp (slope compensation)

can eliminate such problems without drastically

affecting the overall performance of the system.

2.3 Circuit layout and other considerations

The electronic noise generated by any switch-

mode power supply can cause severe stability

problems if the circuit is not layed-out (wired)

properly. A few simple layout practices will help

to minimize noise problems.

When building prototype breadboards, never use

plug-in protoboards or wire wrap construction.

For best results, do all breadboarding on double

sided PCB using ground plane techniques. Keep

all traces and lead lengths to a minimum. Avoid

large loops and keep the area enclosed within

any loops to a minimum. Use common point

grounding techniques and separate the power

ground traces from the signal ground traces.

Locate the control IC and circuitry away from

switching devices and magnetics. Also, the tim-

ing capacitor’s ground connection must be right

at pin 5 as shown in Figure 15. These grounding

and wiring techniques are very important be-

cause the resistance and inductance of the traces

are significant enough to generate noise glitches

which can disrupt the normal operation of the IC.

Also, to provide a low impedance path for high

frequency noise, VCC and VREF should be

decoupled to IC ground with 0.1

µF capacitors.

Additional decoupling in other sensitive areas

may also be necessary. It is very important to

locate the decoupling capacitors as close as

possible to the circuit being decoupled.

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