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AD9480

Rev. A | Page 18 of 28

External Reference

An external reference can be used for greater accuracy and

temperature stability when required. The gain of the AD9480

can also be varied using this configuration. A voltage output

DAC can be used to set VREF, providing for a means to digitally

adjust the full-scale voltage. VREF can be externally set to

voltages from 0.75 V to 1.5 V; optimum performance is typically

obtained at VREF = 1 V. (See the Typical Performance

Characteristics section.)

MAY REQUIRE

RC FILTER

AVDD

EXTERNAL

REFERENCE OR

DAC INPUT

VREF

SENSE

Figure 38. External Reference

Programmable Reference

The programmable reference can be used to set a differential

input span anywhere between 0.75 V p-p and 1.5 V p-p by

using an external resistor divider. The sense pin will self-bias to

0.5 V, and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is

recommended to keep the sum of R1 + R2 ≥ 10 kΩ to limit

VREF loading (for VREF = 1.5 V, set R1 equal to 7 kΩ and R2

equal to 3.5 kΩ).

0.1

µF

VREF

SENSE

Figure 39. Programmable Reference

DIGITAL OUTPUTS

LVDS outputs are available when a 3.7 kΩ RSET resistor is

placed at Pin 42 (LVDSBIAS) to ground. The RSET resistor

current (~1.2 V/RSET) is ratioed on-chip, setting the output

current at each output equal to a nominal 3.5 mA with an RSET

of 3.74 kΩ. Varying the RSET current also linearly changes the

LVDS output current, resulting in a variable output swing for a

fixed termination resistance.

A 100 Ω differential termination resistor placed at the LVDS

receiver inputs results in a nominal 350 mV swing at the

receiver. LVDS mode facilitates interfacing with LVDS receivers

in custom ASICs and FPGAs that have LVDS capability for

superior switching performance in noisy environments. Single

point-to-point net topologies are recommended with a 100 Ω

termination resistor as close to the receiver as possible. Keep the

trace length 3 inches to 4 inches maximum and the differential

output trace lengths as equal as possible.

OUTPUT CODING

Table 10.

Code

(VIN+) − (VIN−)

Offset Binary

Twos Complement

255

>+0.512 V

1111 1111

0111 1111

255

+0.512 V

1111 1111

0111 1111

254

+0.508 V

1111 1110

0111 1110

•

129

+0.004 V

1000 0001

0000 0001

128

+0.0 V

1000 0000

0000 0000

127

–0.004 V

0111 1111

1111 1111

•

−0.504 V

0000 0010

1000 0010

−0.508 V

0000 0001

1000 0001

−0.512 V

0000 0000

1000 0000

<−0.512 V

0000 0000

1000 0000

INTERLEAVING TWO AD9480s

Instrumentation applications may prefer to interleave or ping-

pong two AD9480s to achieve twice the sample rate, or

500 MSPS. In these applications, it is important to match the

gain and offset of the two ADCs. Varying the reference voltage

allows the gain of the ADCs to be adjusted; external dc offset

compensation can be used to reduce offset mismatch between

two ADCs. The sampling phase offset between the two ADCs is

extremely important as well and requires very low skew

between clock signals driving the ADCs (<2 ps clock skew for a

100 MHz analog input frequency).

DATA CLOCK OUT

An LVDS data clock is available at DCO+ and DCO−. These

clocks can facilitate latching off-chip, providing a low skew

clocking solution. The on-chip delay of the DCO clocks tracks

with the on-chip delay of the data bits (under similar loading),

such that the variation between TPD and TCPD is minimized. It is

recommended to keep the trace lengths on the data and DCO

pins matched and to 3 inches to 4 inches maximum. The output

and DCO outputs should be designed for a differential

characteristic impedance of 100 Ω and terminated differentially

at the receiver with 100 Ω.

POWER-DOWN

The chip can be placed in a low power state by driving the

PDWN pin to logic high. Typical power-down dissipation is

15 mW. The data outputs and DCO outputs are high impedance

in power-down state. The time it takes to go into power-down

from assertion of PDWN is one cycle; recovery from power-

down is accomplished in three cycles.

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