ADAU1461WBCPZ-R7 datasheet(45/89 Pages) AD

45 / 89 page

ADAU1461

Rev. 0 | Page 44 of 88

NUMERIC FORMATS

DSP systems commonly use a standard numeric format.

Fractional numeric systems are specified by an A.B format,

where A is the number of bits to the left of the decimal point

and B is the number of bits to the right of the decimal point.

The ADAU1461 uses numeric format 5.23 for both the

parameter and data values.

Numeric Format 5.23

Linear range: −16.0 to (+16.0 − 1 LSB)

Examples:

1000 0000 0000 0000 0000 0000 0000 = −16.0

1110 0000 0000 0000 0000 0000 0000 = −4.0

1111 1000 0000 0000 0000 0000 0000 = −1.0

1111 1110 0000 0000 0000 0000 0000 = −0.25

1111 1111 0011 0011 0011 0011 0011 = −0.1

1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0)

0000 0000 0000 0000 0000 0000 0000 = 0

0000 0000 1100 1100 1100 1100 1101 = 0.1

0000 0010 0000 0000 0000 0000 0000 = 0.25

0000 1000 0000 0000 0000 0000 0000 = 1.0

0010 0000 0000 0000 0000 0000 0000 = 4.0

0111 1111 1111 1111 1111 1111 1111 = (16.0 − 1 LSB)

The serial port accepts up to 24 bits on the input and is sign-

extended to the full 28 bits of the DSP core. This allows internal

gains of up to 24 dB without internal clipping.

A digital clipper circuit is used between the output of the DSP

core and the DACs or serial port outputs (see Figure 68). This

circuit clips the top four bits of the signal to produce a 24-bit

output with a range of 1.0 (minus 1 LSB) to −1.0. Figure 68

shows the maximum signal levels at each point in the data flow

in both binary and decibel levels.

4-BIT SIGN EXTENSION

DATA IN

1.23

(0dB)

1.23

(0dB)

1.23

(0dB)

5.23

(24dB)

5.23

(24dB)

SERIAL

PORT

SIGNAL

PROCESSING

(5.23 FORMAT)

DIGITAL

CLIPPER

Figure 68. Numeric Precision and Clipping Structure

PROGRAMMING

On power-up, the ADAU1461 must be configured with a clock-

ing scheme and then loaded with register settings. After the codec

signal path is set up, the DSP core can be programmed. There

are 1024 instruction cycles per audio sample, resulting in an

internal clock rate of 49.152 MHz when fS = 48 kHz.

The part can be programmed easily using SigmaStudio, a graphical

tool provided by Analog Devices (see Figure 69). No knowledge

of writing line-level DSP code is required. More information

about SigmaStudio can be found at www.analog.com.

Figure 69. SigmaStudio Screen Shot

ADAU1461WBCPZ-R7 Datenblatt(PDF) 45 Page - Analog Devices

ADAU1461WBCPZ-R7 Datenblatt(HTML) 45 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Datenblatt Download

Link URL