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DETAILED DESCRIPTION

Output Enable Glitch Suppression Circuit

CLK

CLK

a) Enable Mode

b) Disable Mode

CDCVF310

SCAS771A – AUGUST 2004 – REVISED AUGUST 2004

The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the

clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative

edge triggered by the input clock) (see Figure 1).

predictable operation.

Figure 1. Enable and Disable Mode Relative to CLK

↓

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