AD7667AST datasheet(17/29 Pages) AD

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AD7667

Rev. 0 | Page 16 of 28

CIRCUIT INFORMATION

SWA

COMP

SWB

REF

REFGND

LSB

MSB

32,768C

INGND

16,384C

65,536C

CONTROL

LOGIC

SWITCHES

CONTROL

BUSY

OUTPUT

CODE

CNVST

Figure 24. ADC Simplified Schematic

The AD7667 is a very fast, low power, single supply, precise

16-bit analog-to-digital converter (ADC). The AD7667 features

different modes to optimize performance according to the

applications. In Warp mode, the part can convert 1 million

samples per second (1 MSPS).

The AD7667 provides the user with an on-chip track/hold,

successive approximation ADC that does not exhibit any

pipeline or latency, making it ideal for multiple multiplexed

channel applications.

The AD7667 can be operated from a single 5 V supply and can

be interfaced to either 5 V or 3 V digital logic. It is housed in

either a 48-lead LQFP or a 48-lead LFCSP that saves space and

allows flexible configurations as either a serial or parallel inter-

face. The AD7667 is pin-to-pin compatible with PulSAR ADCs

and is an upgrade of the AD7666 and AD7661.

CONVERTER OPERATION

The AD7667 is a successive-approximation ADC based on a

charge redistribution DAC. Figure 24 shows a simplified sche-

matic of the ADC. The capacitive DAC consists of an array of

16 binary weighted capacitors and an additional LSB capacitor.

The comparator’s negative input is connected to a dummy

capacitor of the same value as the capacitive DAC array.

During the acquisition phase, the common terminal of the array

tied to the comparator’s positive input is connected to AGND

via SWA. All independent switches are connected to the analog

input IN. Thus, the capacitor array is used as a sampling

capacitor and acquires the analog signal on IN. Similarly, the

dummy capacitor acquires the analog signal on INGND.

When CNVST goes LOW, a conversion phase is initiated. When

the conversion phase begins, SWA and SWB are opened. The

capacitor array and dummy capacitor are then disconnected

from the inputs and connected to REFGND. Therefore, the

differential voltage between IN and INGND captured at the end

of the acquisition phase is applied to the comparator inputs,

causing the comparator to become unbalanced. By switching

each element of the capacitor array between REFGND and REF,

the comparator input varies by binary weighted voltage steps

(VREF/2, VREF/4, …VREF/65536). The control logic toggles these

switches, starting with the MSB, to bring the comparator back

into a balanced condition.

After this process is completed, the control logic generates the

ADC output code and brings the BUSY output LOW.

Modes Of Operation

The AD7667 features three modes of operation: Warp, Normal,

and Impulse. Each mode is best suited for specific applications.

Warp mode allows the fastest conversion rate, up to 1 MSPS.

However in this mode and this mode only, the full specified

accuracy is guaranteed only when the time between conversions

does not exceed 1 ms. If the time between two consecutive

conversions is longer than 1 ms (e.g., after power-up), the first

conversion result should be ignored. This mode makes the

AD7667 ideal for applications where both high accuracy and

fast sample rate are required.

Normal mode is the fastest mode (800 kSPS) without any

limitations on the time between conversions. This mode makes

the AD7667 ideal for asynchronous applications such as data

acquisition systems, where both high accuracy and fast sample

rate are required.

Impulse mode, the lowest power dissipation mode, allows power

saving between conversions. When operating at 1 kSPS, for

example, it typically consumes only 130 µW. This feature makes

the AD7667 ideal for battery-powered applications.

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