AD7938BCPZ datasheet(19/36 Pages) AD

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Data Sheet

AD7938/AD7939

Rev. D | Page 19 of 36

100...000

011...111

1LSB = 2× VREF/4096 (AD7938)

1LSB = 2× VREF/1024 (AD7939)

–VREF +1 LSB

VREF

+VREF –1 LSB

100...001

100...010

011...110

000...001

000...000

111...111

Figure 18. AD7938/AD7939 Ideal Transfer Characteristic

with Twos Complement Output Coding and 2 × VREF Range

TYPICAL CONNECTION DIAGRAM

Figure 19 shows a typical connection diagram for the

AD7938/AD7939. The AGND and DGND pins are connected

together at the device for good noise suppression. The

VREFIN/VREFOUT pin is decoupled to AGND with a 0.47 μF

capacitor to avoid noise pickup if the internal reference is used.

Alternatively, VREFIN/VREFOUT can be connected to an external

reference source. In this case, the reference pin should be

decoupled with a 0.1 μF capacitor. In both cases, the analog

input range can either be 0 V to VREF (RANGE bit = 0) or 0 V to

2 × VREF (RANGE bit = 1). The analog input configuration can

be either eight single-ended inputs, four differential pairs, four

pseudo differential pairs, or seven pseudo differential inputs

(see Table 10). The VDD pin is connected to either a 3 V or 5 V

supply. The voltage applied to the VDRIVE input controls the

voltage of the digital interface. Here, it is connected to the same

3 V supply of the microprocessor to allow a 3 V logic interface

(see the Digital Inputs section).

0.1µF

10µF

3V/5V

SUPPLY

AD7938/AD7939

0.1µF

0.1µF EXTERNAL VREF

0.47µF INTERNAL VREF

AGND

DGND

W/B

CLKIN

VDRIVE

VDD

VREFIN/VREFOUT

10µF

2.5V

VREF

CONVST

BUSY

DB0

DB11/DB9

0 TO VREF/

0 TO 2 × VREF

VIN0

VIN7

Figure 19. Typical Connection Diagram

ANALOG INPUT STRUCTURE

Figure 20 shows the equivalent circuit of the analog input

structure of the AD7938/AD7939 in differential/pseudo

differential mode. In single-ended mode, VIN− is internally

tied to AGND. The four diodes provide ESD protection for the

analog inputs. Care must be taken to ensure that the analog

input signals never exceed the supply rails by more than

300 mV. Doing so causes these diodes to become forward-

biased and start conducting into the substrate. These diodes can

conduct up to 10 mA without causing irreversible damage to

the part.

The C1 capacitors in Figure 20 are typically 4 pF and can

primarily be attributed to pin capacitance. The resistors are

lumped components made up of the on resistance of the

switches. The value of these resistors is typically about 100 Ω.

The C2 capacitors are the sampling capacitors of the ADC and

typically have a capacitance of 45 pF.

For ac applications, removing high frequency components from

the analog input signal is recommended by the use of an RC

low-pass filter on the relevant analog input pins. In applications

where harmonic distortion and signal-to-noise ratio are critical,

the analog input should be driven from a low impedance

source. Large source impedances significantly affect the ac

performance of the ADC. This may necessitate the use of an

input buffer amplifier. The choice of the op amp is a function of

the particular application.

VIN+

VDD

VIN–

VDD

Figure 20. Equivalent Analog Input Circuit,

Conversion Phase: Switches Open, Track Phase: Switches Closed

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of THD that can be

tolerated. The THD increases as the source impedance increases

and performance degrades. Figure 21 and Figure 22 show a

graph of the THD vs. source impedance with a 50 kHz input

tone for both VDD = 5 V and 3 V in single-ended mode and fully

differential mode, respectively.

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