LT1681 datasheet(12/20 Pages) LINER

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LT1681

1681f

translate the optocoupler information. The bandwidths of

the optocoupler and amplifier should be as high as pos-

sible to simplify system compensation. This high band-

width operation is accomplished by using the error ampli-

fier as a transimpedance amplifier, with the optocoupler

transistor emitter providing feedback information directly

into the VFB pin. A resistor from VFB to ground provides the

DC bias condition for the optocoupler. Connecting the

optocoupler transistor collector to the local 5VREF supply

reduces Miller capacitance effects and maximizes the band-

width of the optocoupler. Higher optocoupler current also

means higher bandwidth, and the 5VREF supply can pro-

vide collector currents up to 10mA.

APPLICATIO S I FOR ATIO

Figure 3 is a plot of oscillator frequency vs CFSET and

RFSET. Typical values for 300kHz operation (150kHz sys-

tem frequency) are CFSET = 150pF and RFSET = 51k.

VFB

5VREF

VOUT

SENSE

1.25V

1681 F01

LT1681

Figure 2. Optocoupler High BW Configuration

Oscillator Frequency Programming

and Synchronization

The LT1681 internal oscillator runs at twice the system

switching frequency. The oscillator output toggles a T flip-

flop, generating a 50% duty cycle pulse that is used

internally as the system clock for the IC. Free-run fre-

quency for the internal oscillator is programmed via an RC

timing network connected to the FSET pin. A pull-up

resistor RFSET, connected from the 5VREF pin to FSET,

provides current to charge a timing capacitor CFSET con-

nected from the FSET pin to ground. The oscillator oper-

ates by allowing RFSET to charge CFSET up to 2.5V at which

point RFSET is pulled back toward ground by a 2.5k resistor

internal to the LT1681. When the voltage across CFSET is

pulled down to 1.5V, the FSET pin becomes high imped-

ance, once again allowing RFSET to charge CFSET.

TIMING RESISTOR (k

Ω)

100

150

250

300

350

600

450

1681 F03

200

500

550

400

100

330pF

150pF

100pF

200pF

Figure 3. Oscillator Frequency vs Timing Components

Due the relatively fast fall time of the oscillator waveform,

the FSET pin is held at its 1.5V threshold by an internal low-

impedance clamp to reduce undershoot error. If this pin is

externally forced low for any reason, external current

limiting is required to prevent damage to the LT1681.

Continuous source current from the FSET pin should not

exceed 1mA. Putting a 2k resistor in series with any low

impedance pull-down device will assure proper function

and protect the IC from damage.

Oscillator Synchronization

Synchronization of the LT1681 system clock is accom-

plished by driving a TTL level logic pulse train at the

desired system switching frequency into the SYNC pin. In

order to assure proper synchronization, each phase of the

synchronization signal must be less then an oscillator

free-run cycle.

The SYNC input pulse controls the phasing as well as the

frequency of controller switching. The SYNC circuit func-

tions by forcing the phase of the oscillator output flip-flop

to match the phase of the SYNC pulse and prematurely

ending the oscillator charge cycle on each transition

edge. At the SYNC low-to-high transition, the LT1681

starts a switch-on cycle and the minimum switch-off

period is forced during the SYNC logic low period.

Because the SYNC logic low period corresponds directly

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