DESCRIPTION
The TC514256AP/AJ/AZ is the new generation dynamic RAM organized 262,144 words by 4 bits.
The TC514256AP/AJ/AZ utilizes TOSHIBA's CMOS Silicon gate process technology as well as advanced
circuit techniques to provide wide operating margins, both internally and to the system user.
Multiplexed address inputs permit the TC514256AP/AJ/AZ to be packaged in a standard 20 pin plastic
DIP, 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The package size provides high system bit
densities and is compatible with widely available automated testing and insertion equipment.
oriented features include single power supply of 5V±10% tolerance, direct interfacing capability with
high performance logic families such as Schottky TTL.
System

FEATURES
262,144 word by 4 bit organization
Fast access time and cycle time
trai
TAA
teac
tac
Columuess
Acces inse
CAS Access Time
Cycle Time
Fast Page Mode
Cycle Time
TCS14256AP/AJAZ-701-801-10
80ns
70ns
35ns
20ns
130ns
40ns
40ns
20ns
150ns
45ns
Single power supply of 5V±10%
with a built-in VBB generator
100ns
50ns
25ns
180ns
55ns
• Low Power
440mW MAX. Operating
(TC514256AP/AJ/AZ-70)
385mW MAX. Operating
(TC514256AP/ĀJ/AZ-80)
330mW MAX. Operating
(TC514256AP/AJ/AZ-10)
5.5mW MAX. Standby
Outputs unlatched at cycle end allows two-
dimensional chip selection
Read-Modify-Write, CAS before RAS refresh,
RAS-only refresh, Hidden refresh, and Fast
Page Mode capability
All inputs and outputs TTL compatible
512 refresh cycles/8ms
• Package
TC514256AP : DIP20-P-300B
TC514256AJ : SOJ26-P-300
TC514256AZ : ZIP20-P-400