DESCRIPTION

The TCs142s6P/J/Z is the new generation dynamic RAM organized 262,144 words by 4
bit. The TCs142s6P/J/Z utilizes TOSHIBA's CMOS Silicon gate process technology as well
as advanced circuit techniques to provide wide operating margins, both internally and to
the system user. Multiplexed address inputs permit the TCs142s6P/J/Z to be packaged in a
standard 20 pin plastic DIP and 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The
package size provides high system bit densities and is compatible with widely available
automated testing and insertion equipment. System oriented features include single power
supply of 5V±10% tolerance, direct interfacing capability with high performance logic
families such as Schottky TTL.

FEATURES
• 262,144 words by 4 bit organization
• Fast access time and cycle time
TC5l42s6P/J/Z-Bs-lO-12
tRAC R:AS Access Time B5ns lOOns l20ns
tAA Column Address 45n9 SOns 60ns Access Time
tCAC CAS Access Time 30ns 30ns 35ns
tRC Cycle Time l65ns 190ns 220ns
tpc Fast Page Mode SOns ssns 70ns Cycle Time
• Single power supply of sV±lO% with a builtin VBB generator
• Low Power
4l3mW MAX. Operating(TCs14256P/J/Z-Bs)
3sBmW MAX. Operating(TCs142s6P/J/Z-lO)
303mW MAX. Operating(TCs142s6P/J/Z-12)
s.smW MAX. Standby
• Output unlatched at cycle end allows
two-dimensional chip selection
• Read-Modify-Write, CAS before RAS
refresh, RAS-only refresh, Hidden
refresh, and Fast P~ge Mode capability
• All inputs and outputs TTL compatible
• 512 refresh cycles/Bms
• Package Plastic DIP: TCs142s6P
Plastic SOJ: TCs14256J
Plastic ZIP: TCs14256Z