AD8450ASTZ datasheet(24/42 Pages) AD

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Data Sheet

AD8450

Rev. B | Page 23 of 41

PROGRAMMABLE GAIN INSTRUMENTATION

AMPLIFIER (PGIA)

Figure 51 is a block diagram of the PGIA, which is used to monitor

the battery current. The architecture of the PGIA is the classic

3-op-amp topology, similar to the Analog Devices industry-

standard AD8221 and AD620. This architecture provides the

highest achievable CMRR at a given gain, enabling high-side

battery current sensing without the introduction of significant

errors in the measurement. For more information about instru-

mentation amplifiers, see A Designer's Guide to Instrumentation

Amplifiers.

10kΩ

20kΩ

10kΩ

806Ω

PGIA

+/–

RGP

ISGP0,

ISGP1,

ISGP2,

ISGP3

ISGN0,

ISGN1,

ISGN2,

ISGN3

RGN

ISVN

ISVP

CONNECT

FOR DESIRED

GAIN

+ CURRENT

SHUNT

– CURRENT

SHUNT

ISMEA

G = 2 SUBTRACTOR

100kΩ

19.2kΩ

ISREFH

ISREFL

VREF

POLARITY

INVERTER

POLARITY

INVERTER

MODE

RFBP

–

RFBN

–

GAIN

NETWORKS

(4)

Figure 51. PGIA Simplified Block Diagram

Gain Selection

The PGIA includes four fixed internal gain options. The PGIA

can also use an external gain network for arbitrary gain selection.

The internal gain options are established via four independent

three-resistor networks, which are laser trimmed to a matching

level better than ±0.1%. The internal gains are optimized to

minimize both PGIA gain error and gain error drift, allowing

the controller to set a stable charge/discharge current over

temperature. If the built in internal gains are not adequate, the

PGIA gain can be set via an external three-resistor network.

The internal gains of the PGIA are selected by tying the inverting

inputs of the PGIA preamplifiers (RGP and RGN pins) to the

corresponding gain pins of the internal three-resistor network

(ISGP[0:3] and ISGN[0:3] pins). For example, to set the PGIA

gain to 26, tie the RGP pin to the ISGP0 pin, and tie the RGN

pin to the ISGN0 pin. See Table 5 for information about the

gain selection connections.

The external PGIA gain is set by tying 10 kΩ feedback resistors

between the inverting inputs of the PGIA preamplifiers (RGP and

RGN pins) and the outputs of the PGIA preamplifiers (RFBP and

RFBN pins) and by tying a gain resistor (RG) between the RGP

and RGN pins. When using external resistors, the PGIA gain is

Gain = 2 × (1 + 20 kΩ/RG)

Note that the PGIA subtractor has a closed-loop gain of 2 to

increase the common-mode range of the preamplifiers.

Reversing Polarity When Charging and Discharging

Figure 50 shows that during the charge cycle, the power converter

feeds current into the battery, generating a positive voltage across

the current sense resistor. During the discharge cycle, the power

converter draws current from the battery, generating a negative

voltage across the sense resistor. In other words, the battery current

polarity reverses when the battery discharges.

In the constant current (CC) control loop, this change in

polarity can be problematic if the polarity of the target current

is not reversed. To solve this problem, the AD8450 PGIA includes

a multiplexer preceding its inputs that inverts the polarity of the

PGIA gain. This multiplexer is controlled via the MODE pin.

When the MODE pin is logic high (charge mode), the PGIA gain

is noninverting, and when the MODE pin is logic low (discharge

mode), the PGIA gain is inverting.

PGIA Offset Option

As shown in Figure 51, the PGIA reference node is connected

to the ISREFL and ISREFH pins via an internal resistor divider.

This resistor divider can be used to introduce a temperature

insensitive offset to the output of the PGIA such that the PGIA

output always reads a voltage higher than zero for a zero differ-

ential input. Because the output voltage of the PGIA is always

positive, a unipolar ADC can digitize it.

When the ISREFH pin is tied to the VREF pin with the ISREFL

pin grounded, the voltage at the ISMEA pin is increased by

20 mV, guaranteeing that the output of the PGIA is always

positive for zero differential inputs. Other voltage shifts can be

realized by tying the ISREFH pin to an external voltage source.

The gain from the ISREFH pin to the ISMEA pin is 8 mV/V.

For zero offset, tie the ISREFL and ISREFH pins to ground.

Battery Reversal and Overvoltage Protection

The AD8450 PGIA can be configured for high-side or low-side

current sensing. If the PGIA is configured for high-side current

sensing (see Figure 50) and the battery is connected backward,

the PGIA inputs may be held at a voltage that is below the

negative power rail (AVEE), depending on the battery voltage.

To prevent damage to the PGIA under these conditions, the

PGIA inputs include overvoltage protection circuitry that allows

them to be held at voltages of up 55 V from the opposite power

rail. In other words, the safe voltage span for the PGIA inputs

extends from AVCC − 55 V to AVEE + 55 V.

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