AD8451 datasheet(22/33 Pages) AD

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Data Sheet

AD8451

6. The CV loop tries to pull the VINT node down to reduce

the charging current (IBAT) and prevent the battery voltage

from rising any further. At the same time, the CC loop tries

to keep the VINT node at its current voltage to keep the

battery current at IBAT_SS.

7. Because the loop amplifiers can only pull the VINT node

down due to the analog NOR circuit, the CV loop takes

control of the charging feedback loop, and the CC loop is

disabled.

The analog NOR (minimum output selector) circuit that couples

the outputs of the loop amplifiers is optimized to minimize the

transition time from CC to CV control. Any delay in the transition

causes the CC loop to remain in control of the charge feedback

loop after the battery voltage reaches its target value. Therefore,

the battery voltage continues to rise beyond VBAT_SS until the

control loop transitions; that is, the battery voltage overshoots

its target voltage. When the CV loop takes control of the charge

feedback loop, it reduces the battery voltage to the target voltage.

A large overshoot in the battery voltage due to transition delays

can damage the battery; thus, it is crucial to minimize delays by

implementing a fast CC to CV transition.

Figure 48 is the functional block diagram of the AD8451 CC

and CV feedback loops for discharge mode (MODE logic pin is

low). In discharge mode, the feedback loops operate in a similar

manner as in charge mode. The only difference is in the CV

loop amplifier, which operates as a noninverting integrator in

discharge mode. For illustration purposes, the external networks

connected to the loop amplifiers are simple RC networks

configured to form single-pole integrators (see Figure 48).

Compensation

In battery formation and test systems, the CC and CV feedback

loops have significantly different open-loop gain and crossover

frequencies; therefore, each loop requires its own frequency

compensation. The active filter architecture of the AD8451 CC

and CV loops allows the frequency response of each loop to be

set independently via external components. Moreover, due to

the internal switches in the CC and CV amplifiers, the frequency

response of the loops in charge mode does not affect the

frequency response of the loops in discharge mode.

Unlike simpler controllers that use passive networks to ground

for frequency compensation, the AD8451 allows the use of

feedback networks for its CC and CV loop filter amplifiers.

These networks enable the implementation of both

proportional differentiator (PD) Type II and proportional

integrator differentiator (PID) Type III compensators. Note

that in charge mode, both the CC and CV loops implement

inverting compensators, whereas in discharge mode, the CC

loop implements an inverting compensator, and the CV loop

implements a noninverting compensator. As a result, the CV loop

in discharge mode includes an additional amplifier, VSET buffer, to

buffer the VSET node from the feedback network (see Figure 48).

VINT Buffer

The unity-gain amplifier (VINT buffer) is a clamp amplifier

that drives the VCTRL pin. The VCTRL pin is the control

output of the AD8451 and the control input of the power

converter (see Figure 46 and Figure 48). The output voltage

range of this amplifier is bounded by the clamp voltages at the

VCLP and VCLN pins such that

VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V

The reduction in the output voltage range of the amplifier is a

safety feature that allows the AD8451 to drive devices such as

the ADP1972 PWM controller, whose input voltage range must

not exceed 5.5 V (that is, the voltage at the COMP pin of the

ADP1972 must be below 5.5 V).

MODE PIN, CHARGE AND DISCHARGE CONTROL

The MODE pin is a TTL logic input that configures the AD8451

for either charge or discharge mode. A logic low (VMODE < 0.8 V)

corresponds to discharge mode, and a logic high (VMODE > 2 V)

corresponds to charge mode. Internal to the AD8451, the MODE

pin toggles all single-pole, double throw (SPDT) switches in the

CC and CV loop amplifiers and inverts the gain polarity of the IA.

VSET

BUFFER

VSETBF

ISET

–

CC LOOP

AMPLIFIER

CV LOOP

AMPLIFIER

IVE0

VVE0

ANALOG

‘NOR’

ISVN

BVP

BVN

GDA

–

GIA

ISMEAS

BVMEA

IBAT

VVP0

1×

VCTRL

VCLN

VCLP

VINT

BUFFER

VBAT

SENSE

RESISTOR

MODE

–

VINT

ISVP

MINIMUM

OUTPUT

SELECTOR

V3 < VCTRL < V4

1×

POWER

CONVERTER

IOUT

VCTRL

CURRENT

POWER

BUS

Figure 48. Functional Block Diagram of the CC and CV Loops in Discharge Mode (MODE Pin Low)

Rev. 0 | Page 21 of 32

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