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AD8451

Data Sheet

In constant voltage mode, when the CV feedback loop is in

steady state, the VSET input sets the battery voltage as follows:

VBAT_SS =

VSET

where GDA is the DA gain.

Therefore, the accuracy and temperature stability of the formation

and test system are not only dependent on the precision of the

AD8451, but also on the accuracy of the ISET and VSET inputs.

LOOP FILTER AMPLIFIERS

The AD8451 has two loop filter amplifiers, also known as error

amplifiers (see Figure 49). One amplifier is for constant current

control (CC loop filter amplifier), and the other amplifier is for

constant voltage control (CV loop filter amplifier). The outputs

of these amplifiers are combined using a minimum output

selector circuit to perform automatic CC to CV switching.

Table 5 lists the inputs of the loop filter amplifiers for charge

mode and discharge mode.

Table 5. Integrator Input Connections

Feedback Loop Function

Reference

Input

Feedback

Terminal

Control the Current While Discharging

a Battery

ISET

IVE0

Control the Current While Charging

a Battery

ISET

IVE1

Control the Voltage While Discharging

a Battery

VSET

VVE0

Control the Voltage While Charging

a Battery

VSET

VVE1

The CC and CV amplifiers in charge mode and the CC amplifier

in discharge mode are inverting integrators, whereas the CV

amplifier in discharge mode is a noninverting integrator. Therefore,

the CV amplifier in discharge mode uses an extra amplifier, the

VSET buffer, to buffer the VSET input pin (see Figure 42). In

addition, the CV amplifier in discharge mode uses the VVP0

pin to couple the signal from the BVMEA pin to the integrator.

CONNECTING TO A PWM CONTROLLER (VCTRL PIN)

The VCTRL output pin of the AD8451 is designed to interface

with linear power converters and with PWM controllers such as

the ADP1972. The voltage range of the VCTRL output pin is

bound by the voltages at the VCLP and VCLN pins, as follows:

VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V

Because the maximum rated input voltage at the COMP pin of

the ADP1972 is 5.5 V, connect the clamp voltages of the output

amplifier to 5 V (VCLP) and ground (VCLN) to prevent over-

ranging of the COMP input. As an additional precaution, install

an external 5.1 V Zener diode from the COMP pin to ground

with a series 1 kΩ resistor connected between the VCTRL and

COMP pins. Consult the ADP1972 data sheet for additional

applications information.

Given the architecture of the AD8451, the controller requires

that an increasing voltage at the VCTRL pin translates to a

larger output current in the power converter. If this is not the

case, a unity-gain inverting amplifier can be added in series

with the AD8451 output to add an extra inversion.

STEP-BY-STEP DESIGN EXAMPLE

This section describes the systematic design of a 1 A battery

charger/discharger using the AD8451 controller and the

ADP1972 PWM controller. The power converter used in this

design is a nonisolated buck boost dc-to-dc converter. The target

battery is a 4.2 V fully charged, 2.7 V fully discharged Li-Ion

battery.

Step 1: Design the Switching Power Converter

Select the switches and passive components of the buck boost

power converter to support the 1 A maximum battery current.

The design of the power converter is beyond the scope of this

data sheet; however, there are many application notes and other

helpful documents available from manufacturers of integrated

driver circuits and power MOSFET output devices that can be

used for reference.

Step 2: Identify the Control Voltage Range of the

ADP1972

The control voltage range of the ADP1972 (voltage range of the

COMP input pin) is 0.5 V to 4.5 V. An input voltage of 4.5 V

results in the highest duty cycle and output current, whereas an

input voltage of 0.5 V results in the lowest duty cycle and output

current. Because the COMP pin connects directly to the VCTRL

output pin of the AD8451, the battery current is proportional to

the voltage at the VCTRL pin.

For information about how to interface the ADP1972 to the

power converter switches, see the ADP1972 data sheet.

Step 3: Determine the Control Voltage for the CV Loop

The relationship between the control voltage for the CV loop

(the voltage at the VSET pin), the target battery voltage, and the

DA gain is as follows:

CV Battery Target Voltage =

VSET

In charge mode, for a CV battery target voltage of 4.2 V, select a

CV control voltage of 3.36 V. In discharge mode, for a CV

battery target voltage of 2.7 V, select a CV control voltage of

2.16 V.

Rev. 0 | Page 24 of 32

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