5812-DS00-R datasheet(52/84 Pages) BOARDCOM

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BCM5812

Advance Data Sheet

3/11/03

B roa dcom Co rpo rat ion

Page 44

Endian Considerations

Document

5812-DS01-405-R

Figure 39: Typical Big Endian Processor PCI Bus Configuration

For a big endian host processor, clearing CRYPTONET_LE enables most host structures to be constructed without the need

for software bye swapping. This applies to the structures shown in Figure 5 on page 7, and to the ARCFOUR State output.

Byte stream data is unaffected.

NORMAL_PCI would be used in non-standard PCI bus configurations. Figure 40 shows an example of a match bit lanes bus

policy. If NORMAL_PCI is cleared, the BCM5812 byte swaps everything on its way in or out, whether a master or slave

access, including the CSRs.

Table 14: Endian Control Flags

Name

Use

Description

Default

CRYPTONET_LE

Little Endian Host Processor

If zero, swap bytes for MCR, command

context, fragment chain entries, BigNum data

fragments, and ARCFOUR States output using

DMA bus master access.

NORMAL_PCI

Conventional PCI Configuration

If zero, swap bytes for all data read or written

over the PCI bus, master or slave.

7...0

15..8

23..16

31.24

63..56 55.48 47.40 39.32

7...0

15..8

23..16

31.24

7...0

15..8

23..16

31.24

PCI Bus W ord 0

PCI Bus W ord 1

000

001

010

011

100

101

110

111

Byte Address

Bit Num ber

W ord in host m em ory

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