5812-DS00-R datasheet(80/84 Pages) BOARDCOM

80 / 84 page

BCM5812

Advance Data Sheet

3/11/03

B roa dcom Co rpo rat ion

Page 72

Alignment Restrictions

Document

5812-DS01-405-R

Table 31 shows alignment requirements for all memory-resident data in DH/RSA/DSA/modular arithmetic operations.

Table 30: Alignment Restrictions for IPSec/SSL/TLS Crypto/Authentication Operations

Memory-Resident Data Type

Alignment Requirement,

Size Requirement

Packet Payload Data

Input Data Buffers (per Chain Entry)

None (byte)

Output Data Buffers (per Chain Entry)

32-bit

Multiple of 32 bits

Control and Command Structures

Chain Entry descriptors (Input and Output)

32-bit

Fixed (3 words of 32 bits)

Command Context Structures

32-bit

Fixed (depends on operation)

64-bytes minimum is read

Master Command Record Structures

32-bit

(1 + #pkts

∗8) 32-bit words)

Table 31: Alignment Restrictions for DH/RSA/DSA/Modular Arithmetic Operations

Memory-Resident Data Type

Alignment Requirement

Size Requirement

Packet Payload Data

Input Data Buffers (per Chain Entry)

32-bit

Multiple of 32 bits

Output Data Buffers (per Chain Entry)

32-bit

Multiple of 32 bits

Control and Command Structures

Chain Entry descriptors (Input and Output)

32-bit

Fixed (3 words of 32 bits)

Command Context Structure

32-bit

Fixed (depends on operation)

64-bytes minimum is read

Master Command Record

32-bit

(1 + #pkts

∗8) 32-bit words)

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