10

LTC2604/LTC2614/LTC2624

2604f

Table 1.

COMMAND*

C3

C2

C1

C0

0000

Write to Input Register n

0001

Update (Power Up) DAC Register n

0010

Write to Input Register n, Update (Power Up) All n

0011

Write to and Update (Power Up) n

0100

Power Down n

1111

No Operation

ADDRESS (n)*

A3

A2

A1

A0

0000

DAC A

0001

DAC B

0010

DAC C

0011

DAC D

1111

All DACs

OPERATIO

only be transferred to the device when the CS/LD signal is

low.The rising edge of CS/LD ends the data transfer and

causes the device to carry out the action specified in the

24-bit input word. The complete sequence is shown in

Figure 2a.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The first four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register into

the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path and

registers are shown in the block diagram.

While the minimum input word is 24 bits, it may optionally

be extended to 32 bits. To use the 32-bit word width, 8

don’t-care bits are transferred to the device first, followed

by the 24-bit word as just described. Figure 2b shows the

32-bit sequence. The 32-bit word is required for daisy-

chain operation, and is also available to accommodate

microprocessors which have a minimum word width of 16

bits (2 bytes).

Power-On Reset

The LTC2604/LTC2614/LTC2624 clear the outputs to zero

scale when power is first applied, making system initializa-

tion consistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2604/

LTC2614/LTC2624 contain circuitry to reduce the power-

on glitch; furthermore, the glitch amplitude can be made

arbitrarily small by reducing the ramp rate of the power

supply. For example, if the power supply is ramped to 5V

in 1ms, the analog outputs rise less than 10mV above

ground (typ) during power-on. See Power-On Reset Glitch

in the Typical Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pins 3, 6, 12 and 15) should be kept

within the range – 0.3V

Maximum Ratings). Particular care should be taken to

observe these limits during power supply turn-on and

transition.

Transfer Function

The digital-to-analog transfer function is

V

k

REF x REFLO

REFLO

OUT IDEAL

N

()

[–

]

= 







+

2

where k is the decimal equivalent of the binary DAC input

code, N is the resolution and REF x is the voltage at REF A,

REF B, REF C and REF D (Pins 3, 6, 12 and 15).

Serial Interface

The CS/LD input is level triggered. When this input is taken

low, it acts as a chip-select signal, powering-on the SDI

and SCK buffers and enabling the input shift register. Data

(SDI input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded first; then the 4-bit

DAC address, A3-A0; and finally the 16-bit data word. The

data word comprises the 16-, 14- or 12-bit input code,

ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits

(LTC2604, LTC2614 and LTC2624 respectively). Data can

*Command and address codes not shown are reserved and should not be used.