1

PS8502

10/10/00

DIV0

DIV1

HF#

GND

FBIN

GND

OE0

OE1

CLKIN

OUT0

GND

GND

OUT2

OUT3

OE3

OE2

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

AGND

FBOUT

OUT1

Product Features

• Four synchronous outputs

• Selectabledivider/multiplier

• Output Enable control

• Low phase error < 150 ps

• Allows clock input to have spread spectrum modulation for

EMI reduction

• Low output skew < 200 ps

• Low cycle jitter < 200 ps

• Industrialtemperature(–40° Cto85° C)

• 3.3VVsupply

• Packages:24-pinQSOP(Q)and24-pinTSSOP(L)

Product Description

PI6C2310 is a low skew, low jitter, PLL clock buffer with divider or

multiplier designed for PCI-X application in servers and worksta-

tions. There are two selectable input ranges using HF# input: 10-40

MHz and 40-80 MHz. All outputs are synchronized to the input and

to the other outputs. Each output can be independently turned off

to reduce EMI and power consumption.

Block Diagram

Pin Configuration

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PCI-X Clock Buffers

PI6C2310

24-Pin

Q, L

#

F

H1

V

I

D0

V

I

Dx

T

U

ON

I

K

L

Cx

T

U

O

11

1

N

I

K

L

C

z

H

M

3

3

z

H

M

3

3

11

0

N

I

K

L

C

x

2z

H

M

6

6

10

1

N

I

K

L

C

x

3z

H

M

0

0

1

10

0

N

I

K

L

C

x

4z

H

M

3

3

1

01

1

2

/

N

I

K

L

C

z

H

M

6

6

z

H

M

3

3

01

0

N

I

K

L

Cz

H

M

6

6

00

1

N

I

K

L

C

x

5

.

1z

H

M

0

0

1

00

0

N

I

K

L

C

x

2z

H

M

3

3

1

Clock Select Table

OUT0

OUT1

OUT2

OUT3

FBOUT

DIV

OE[0:3]

HF#

CLKIN

FBIN

DIV[0:1]

PLL