USB97C201 datasheet(31/59 Pages) SMSC

31 / 59 page

SMSC DS – USB97C201

Page 31

Rev. 03/25/2002

PRELIMINARY

Table 28 – SIE Status Register

SIE_STAT

(0xB0 - RESET=0x00)

SIE STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

[7]

SET_STALL

R/W

Set to “1” if a SET_FEATURE_ENDPOINT_HALT command

is received on any endpoint by the SIE. Which endpoint is

STALLed can be determined by examining their CTL

registers.

CLR_STALL

R/W

Set

“1”

CLEAR_FEATURE_ENDPOINT_HALT

command is received on any endpoint by the SIE. Which

endpoint’s STALL condition is cleared can be determined

by examining their CTL registers.

SET_CONF

R/W

Set to “1” if a SET_CONFIGURATION command is received

on endpoint 0 by the SIE and the resulting configuration is

set and reported in the USB_CONFIG register.

Reserved

This read only bit always returns the value of “0”.

SET_INTF

R/W

Set to “1” if a SET_INTERFACE command is received on

endpoint 0 by the SIE.

Reserved

R-

This read only bit always returns the value of “0”.

SET_REMWU

R/W

Set

“1”

SET_FEATURE_REMOTE_WAKE_UP

command is received on endpoint 0 by the SIE.

CLR_REMWU

R/W

Set

“1”

CLEAR_FEATURE_ENDPOINT_REMOTE_WAKE_UP

command is received on endpoint 0 by the SIE.

Note: These bits are masked by the SIE_MSK register and OR’d to drive the INT3 interrupt line into the 8051 core.

They may be cleared writing a “1” to the bit location.

Table 29 – SIE Status Mask Register

SIE_MSK

(0xAE - RESET=0xFF)

SIE STATUS MASK REGISTER

BIT

NAME

R/W

DESCRIPTION

[7]

SET_STALL

R/W