USB97C201 datasheet(47/59 Pages) SMSC

47 / 59 page

SMSC DS – USB97C201

Page 47

Rev. 03/25/2002

PRELIMINARY

NAME

CYCLE

IDE_nIOW

STOP

IDE_nIOR

nDMARDY

STROBE

IORDY

STROBE

nDMARDY

Note:

“Ultra ATA/66 Read Cycle”: Data transfers are from the IDE device to the USB97C201.

“Ultra ATA/66 Write Cycle”: Data transfers are from the USB97C201 to the IDE device.

6.3.6

ULTRA ATA/66 OPERATION

After initialization, there are two primary operations provided by the Ultra ATA/66 controller: data transfers and cyclic

redundancy checking (CRC).

6.3.6.1

Initialization

Initialization includes enabling and performing proper set up on the USB97C201and the IDE device. For the

USB97C201, it is necessary to enable Ultra ATA/66 mode for the IDE device and setting up the Ultra ATA/66 cycle

timings through the ATA_DMA register. The USB97C201 supports five timing modes: Mode 0 (120ns cycle time),

Mode 1 (80 ns cycle time), Mode 2 (60ns cycle time), Mode 3 (45ns cycle time), and Mode 4 (30ns cycle time).

6.3.6.2

Data Transfer Operation

The USB97C201 and the Ultra ATA compatible IDE device control the transfer via the Ultra ATA protocol. The

actual data transfer consists of three phases, a start-up phase, a data transfer phase, and a burst termination phase.

Start-Up Phase: The IDE device begins the start-up phase by asserting DRQ signal. When ready to begin the

transfer, the USB97C201 will assert nDACK.

When nDACK is asserted, the USB97C201 will drive CS0/1

inactive, and A0-A2 low.

For Write cycles, the USB97C201 will deassert STOP, wait for the IDE device to assert nDMARDY and then

drive the first data word and the STROBE signal.

For Read cycles, the USB97C201will tristate the data lines, deassert STOP, and assert nDMARDY. The

IDE device will then drive the first data word and the STROBE signal.

Data-Transfer Phase: The burst data transfer continues with the data source (Writes: USB97C201, Reads: IDE

devices) providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and

falling edge of STROBE.

The source can pause the burst stream by holding STROBE high or low, resuming the burst stream by

again toggling STROBE.

The receiver can pause the burst stream by negating the nDMARDY and resumes the transfers by

asserting nDMARDY.

The USB97C201 may pause a burst transaction in order to toggle internal data buffer, or to prevent a buffer over or

under flow condition, resuming once the condition has cleared.

Termination Phase: Either the source or the receiver can terminate a burst transfer. A burst termination

consists of a Stop Request, Stop Acknowledge and transfer of CRC data.

The USB97C201 can stop a burst by asserting STOP, with the IDE device acknowledged by deasserting

DRQ.

The IDE device stops a burst by deasserting DRQ and the USB97C201 acknowledges by asserting STOP.

The source then drives the STROBE signal to a high level. The USB97C201 then drive the CRC value onto

the data lines and deassert nDACK. The IDE devices will latch the CRC value on the rising edge of nDACK.

The USB97C201 will terminate a burst transfer if a Programmed I/O (PIO) cycle is executed to the IDE channel

currently running the burst, or upon transferring the last data from the final PRD.

At the completion of the entire transfer process, the IDE device will issue an interrupt, setting the ATA_IRQ bit and

forcing the remaining data to be sent to host on read operations.

USB97C201 Datenblatt(PDF) 47 Page - SMSC Corporation

USB97C201 Datenblatt(HTML) 47 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datenblatt Download

Link URL