¡ Semiconductor

MSM56V16800E

13/30

Page Read & Write Cycle (Same Bank)

@ CAS Latency = 2, Burst Length = 4

1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write command

to avoid bus contention.

Input data during the precharge input cycle will be masked internally.

CLK

CKE

RAS

CAS

ADDR

DQ

WE

DQM

CS

A11

A10

0123456789

10

11

12

13

14

15

16

17

18

19



















Ca0

Cb0

,



,



Cc0



Cd0

Qa0

Read Command

Write Command

Precharge Command

,







,

,



,



,

,

Bank A Active









































Qa1

Qb0

Qb1

Dc0

Dc1

Dd0

,



,

,





,

,

,,



Read Command

Write Command

High

*Note2

*Note1