ADS5553IPFPR datasheet(6/24 Pages) TI

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ADS5553

SLWS158 − FEBRUARY 2005

www.ti.com

TIMING CHARACTERISTICS

NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing

matches closely with the specified values.

Data Invalid

tSTART

tPDI = tSTART + tsu

N − 17

N − 16

N − 15

N − 14

N − 13

N − 3N − 2N − 1N

tEND

tsu

Data Out

(D0−D11)

Output Clock

Input Clock

Analog

Input

Signal

Sample

N + 1

N + 2

N + 3

N + 4

N + 14

N + 15

N + 16

N + 17

16.5 Clock Cycles

Figure 1. Timing Diagram

TIMING CHARACTERISTICS(3)

Over full temperature range (TMIN = −40°C to TMAX = +85°C), sampling rate = 65 MSPS, 50% clock duty cycle, and AVDD = DRVDD = 3.3 V,

unless otherwise noted

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Switching Specification

Aperture delay, tA

Input CLK falling edge to data sampling point

Aperture delay matching, tA

Channel-to-channel aperture delay matching

Aperture jitter (uncertainty)

Uncertainty in sampling instant

300

Latency

16.5

Clock

Cyles

Data setup time, tsu

Data valid(1) to 50% of CLKOUT rising edge

4.3

Data hold time, th

50% of CLKOUT rising edge to data becoming invalid(1)

2.8

Data start time, tSTART

50% of clock input to beginning of valid data(1)

2.5

4.5

Data stop time, tEND

50% of clock input to end of valid data(1)

10.6

Data rise time, tr

Data rise time measured from 20% to 80% of DRVDD

6.6

Data fall time, tf

Data fall time measured from 80% to 20% of DRVDD

5.5

Data setup time, tsu

Data valid(1) to 50% of CLKOUT rising edge, fS = 40 MSPS

8.5

Data hold time, th

50% of CLKOUT rising edge to data becoming invalid(1),

fS = 40 MSPS

2.6

Data start time, tSTART

50% of clock input to beginning of valid data(1), FS = 40 MSPS

−2.5

Data stop time, tEND

50% of clock input to end of valid data(1), FS = 40 MSPS

11.5

Data rise time, tr

Data rise time measured from 20% to 80% of DRVDD,

fS = 40 MSPS

7.5

Data fall time, tf

Data fall time measured from 80% to 20% of DRVDD,

fS = 40 MSPS

7.3

Output enable (OE) to data output

delay

Time required for outputs to have stable timings with respect to

the input clock(2) after OE is activated

1000

Clock

Cycles

(1) Data valid refers to 2 V for logic high and 0.8 V for logic low.

(2): Data outputs are available within a clock from assertion of OE; however it takes 1000 clock cycles to ensure stable timing with respect to input

clock.

(3): Timing parameters are ensured by design and characterization and not tested in production.

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