ADS5553IPFPR datasheet(19/24 Pages) TI

19 / 24 page

ADS5553

SLWS158 − FEBRUARY 2005

www.ti.com

INPUT VOLTAGE OVER-STRESS

The ADS5553 can handle absolute maximum voltages

of 3.6 V DC on the input pins INP and INM. For DC

inputs between 3.6 V and 3.8 V, a 25 Ω resistor is

required in series with the input pins. For inputs above

3.8 V, the device can handle only transients, which need

to have less than 5% duty cycle of overstress. The input

pins connect internally to an ESD diode to AVDD, as well

as a switched capacitor circuit. The sampling capacitor

of the switched capacitor circuit connects to the input

pins through a switch in the sample phase. In this

phase, an input larger then 2.65 V would cause the

switched capacitor circuit to present an equivalent load

of a forward biased diode to 2.65 V, in series with a 60Ω

impedance. Also, beyond the voltage on AVDD, the ESD

diode to AVDD starts to become forward biased.

In the phase where the sampling switch is off, the diode

loading from the input switched capacitor circuit is

disconnected from the pin, while the ESD loading to

AVDD is still present.

CAUTION:

A violation of any of the previously stated

conditions could damage the device (or reduce

its lifetime) either due to electromigration or

gate oxide integrity. Care should be taken not

to expose the device to input over-voltage for

extended periods of time as it may degrade

device reliability.

POWER SUPPLY SEQUENCE

The preferred mode of power supply sequencing is to

power up AVDD first, followed by DRVDD. Raising both

supplies simultaneously is also a valid power supply

sequence. In the event that DRVDD powers up before

AVDD in the system, AVDD must power up within 10 ms

of DRVDD.

POWER DOWN

The device enters power down in one of two ways:

either by reducing the clock speed to between dc and

1 MHz or by selecting any of the modes in Table 2. If

reducing the clock speed, power-down may be initiated

for any clock frequency below 10 MHz. The actual

frequency at which the device powers down varies from

device to device.

Table 2. Powerdown Mode Selection

PDN

(Pin 50)

OEA

(Pin 52)

OEB

(Pin 48)

Out A

Out B

ADC A

ADC B

Off

REFERENCE CIRCUIT

The ADS5553 has built-in internal reference

generation, requiring no external circuitry on the printed

circuit board (PCB). For optimum performance, it is best

to connect both REFP and REFM to ground with a 1 µF

decoupling capacitor in series with a 20 Ω resistor, as

shown in Figure 32. In addition, an external 56.2-kΩ

resistor should be connected from IREF (pin 10) to

AGND to set the proper current for the operation of the

ADC, as shown in Figure 32. No capacitor should be

connected between pin 31 and ground; only the 56.2 kΩ

resistor should be used.

20 Ω

REFP

REFM

IREF

1 µF

20 Ω

56 kΩ

Figure 32. REFP, REFM, and IREF Connections

for Optimum Performance

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