High Speed CMOS Logic – 54HC02

Quad 2-Input NOR Gates in bare die form

Output Drive Capability: 10 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

 

Die Size (Unsawn)

610 x 610

24 x 24

µm

mils

Minimum Bond Pad Size

85 x 85

3.35 x 3.35

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

Operating Voltage Range: 2V to 6V

Function compatible with 54LS02

High Noise Immunity CMOS process

Full Military Temperature Range.

Rev 1.0

22/04/19

Features:

Description

The 54HC02 2-Input NOR Gate is fabricated on a .35µm

advanced CMOS process combining high speed LSTTL

performance with CMOS low power. The device performs

the Boolean function Y = (A + B) or Y = A • B in positive

logic. Internal circuitry comprises of three stages and

includes buffered output for high noise immunity and

stability. Inputs are compatible with standard CMOS

outputs; with pull-up resistors, they are compatible with

LSTTL outputs. The product die size is significantly smaller

than industry peers due to its re-design and production

using a more advanced CMOS process.

Ordering Information

Die Dimensions in µm (mils)

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

610 (24)

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

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