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HN58V66API-10 Datenblatt(PDF) 21 Page - Renesas Technology Corp |
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HN58V66API-10 Datenblatt(HTML) 21 Page - Renesas Technology Corp |
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21 / 28 page ![]() HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Rev.3.00, Feb.02.2004, page 21 of 26 2. Data protection at VCC on/off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal. VCC CPU RESET Unprogrammable Unprogrammable * * 2.1 Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below. CE VCC × × OE × VSS × WE × × VCC ×: Don’t care. VCC: Pull-up to VCC level. VSS: Pull-down to VSS level. |
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