TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT

TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT

DYNAMIC RAM MODULE

SMMS137E – JANUARY 1991 – REVISEDJUNE 1995

8

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

’248NBK36B-60

’248NBK36B-70

’248NBK36B-80

UNIT

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

VOH

High-level output

voltage

IOH = – 5 mA

2.4

2.4

2.4

V

VOL

Low-level output

voltage

IOL = 4.2 mA

0.4

0.4

0.4

V

II

Input current (leakage)

VCC = 5.5 V,

VI = 0 V to 6.5 V,

All other pins = 0 V to VCC

± 20

± 20

± 20

µA

IO

Output current

(leakage)

VCC = 5.5 V,

VO = 0 V to VCC,

CAS high

± 20

± 20

± 20

µA

ICC1

Read or write cycle

current (see Note 3)

VCC = 5.5 V,

Minimum cycle

963

828

738

mA

ICC2

Standby current

After 1 memory cycle,

RAS and CAS high,

VIH = 2.4 V (TTL)

36

36

36

mA

ICC2

Standby current

After 1 memory cycle,

RAS and CAS high,

VIH = VCC – 0.2 V (CMOS)

18

18

18

mA

ICC3

Average refresh current

(RAS only or CBR)

(see Note 3)

VCC = 5.5 V,

Minimum cycle,

RAS cycling,

CAS high (RAS only),

RAS low after CAS low (CBR)

1890

1620

1440

mA

ICC4

Average page current

(see Note 4)

VCC = 5.5 V,

tPC = minimum,

RAS low, CAS cycling

828

738

648

mA

NOTES:

3. Measured with a maximum of one address change while RAS = VIL

4. Measured with a maximum of one address change while CAS = VIH

capacitance over recommended ranges of supply voltage and operating free-air temperature,

f = 1 MHz (see Note 5)

PARAMETER

’124MBK36B

’248NBK36B

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

Ci(A)

Input capacitance, A0 – A9

45

90

pF

Ci(R)

Input capacitance, RAS

35

35

pF

Ci(C)

Input capacitance, CAS

21

42

pF

Ci(W)

Input capacitance, W

63

126

pF

Co(DQ) Output capacitance on DQ pins

7

14

pF

NOTE 5: VCC = 5 V ± 0.5 V and the bias on pins under test is 0 V.