WM8802SCFV datasheet(38/65 Pages) WOLFSON

38 / 65 page

WM8802

Product Preview

PP Rev 1.1 April 2004

CONTENTS

R/W

CCB

ADDRESS

Function setting data input

write

0xE8

CS data input

write

0xE9

Interrupt data output

read

0xEA

fs data output

read

0xEB

CS data output

read

0xEC

Pc data output

read

0xED

Table 17 Relationship between Register Input/Output Contents and CCB Addresses

DATA WRITE METHOD

Input is performed in the following sequence: CCB addresses of A0 to A3 and B0 to B3, chip

addresses of DI0 and DI1, command addresses of DI4 to DI7 and data of DI8 to DI15. DI2 and DI3

are reserved for the system and should always be set to "0".

For the chip addresses, DI0 corresponds to CAL (low-order) and DI1 corresponds to CAU (high-

order).

DATA READ METHOD

Read data is output from DO. DO is in the high impedance state when CE is Low and begins

outputting at the rising edge of CE after the register address is recognised. DO then returns to the

high impedance state at the falling edge of CE.

If DO outputs using multiple WM8802 units are to be shared the DO outputs of the WM8802 can be

set to in a high impedance state using DOEN, This will prevent any misreading of registers from an

unselected device.

INPUT/OUTPUT TIMINGS

DI0

….

DI15

DI5

DI4

DI3

DI2

DI1

Hi-Z

Figure 30 Input Timing Chart (Normal, Low Clock)

WM8802SCFV Datenblatt(PDF) 38 Page - Wolfson Microelectronics plc

WM8802SCFV Datenblatt(HTML) 38 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datenblatt Download

Link URL