WM8802SCFV datasheet(16/65 Pages) WOLFSON

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WM8802

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PP Rev 1.1 April 2004

When the PLL changes from locked to unlocked status, the timing for switching the clock from the

PLL source to the XIN source can be changed with XTWT[0:1]. It is recommended to use these

commands if noise occurs during clock switching.

CAUTIONS ON SWITCHING CLOCK SOURCE WHILE PLL IS LOCKED

Clock continuity is maintained when switching the clock to the XIN source with SELMTD, OCKSEL,

and RCKSEL. RERR outputs an error (High) when the oscillation amplifier is stopped while the PLL

is locked (initial setting). The oscillation amplifier goes into the operating state at the same time that

the clock is switched to the XIN source and calculation of the input fs (sampling frequency) resumes.

The previous fs calculation value is then reset. The processing performs as if the fs value had

changed compared to the newly calculated fs value.

The following settings must be performed in order to switch the clock source with SELMTD, OCKSEL

and RCKSEL while PLL is locked and maintaining the RERR status.

(1)

Set the oscillation amplifier to the continuous operation mode with AMPOPR[0:1].

(2)

Set with FSERR the mode for not reflecting fs changes to the error flag.

By performing one of the above settings, it is possible to control the RERR change status when

switching the clock source with SELMTD, OCKSEL and RCKSEL.

When switching the clock source to XIN (oscillation amplifier stopped and PLL locked), the output

clock is output after the oscillation amplifier starts operating. When switching the clock source from

XIN to PLL the clock continuity is maintained.

MASTER CLOCK BLOCK DIAGRAM (TMCK, XIN, XOUT, RMCK, XMCK)

The relationships between the three master clocks, switching and the frequency division function are

shown below.

The contents in the square brackets [

∗∗∗] of the switch function blocks correspond to the write

command names.

Lock/Unlock switching is automatically performed through PLL locking/unlocking.

PLL

1/N

(256fs or 512fs)

Selected Biphase

TMCK (I) 256fs only

XIN (I)

XOUT (O)

RMCK (O)

XMCK (O)

[EXSYNC]

[RCKSEL]

[PLLOPR]

[PLLSEL]

[PRSEL1]

[XRSEL1]

[XINSEL]

[XMSEL1]

[AMPOPR1]

(N=1, 2)

Lock /Unlock

1/N

(N=1, 2)

1/N

(N=1, 2, 4)

1/N

(N=1, 2, 4)

[OCKSEL]

[XMSEL0]

[XRSEL0]

[PRSEL0]

[SELMTD]

[AMPOPR0]

Figure 6 Master Clock Block Diagram

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